2 * Author: Thomas Ingleby <thomas.c.ingleby@intel.com>
3 * Copyright (c) 2014 Intel Corporation.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice shall be
14 * included in all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "x86/intel_galileo_rev_d.h"
32 #define UIO_PATH "/dev/uio0"
33 #define PLATFORM_NAME "Intel Galileo Gen 1"
35 static uint8_t *mmap_reg = NULL;
36 static int mmap_fd = 0;
37 static int mmap_size = 0x1000;
38 static unsigned int mmap_count = 0;
41 mraa_intel_galileo_g1_mmap_unsetup()
43 if (mmap_reg == NULL) {
44 syslog(LOG_WARNING, "galileo1: Mmap null register nothing to unsetup");
45 return MRAA_ERROR_INVALID_RESOURCE;
47 munmap(mmap_reg, mmap_size);
54 mraa_intel_galileo_g1_mmap_write(mraa_gpio_context dev, int value)
56 int bitpos = plat->pins[dev->phy_pin].mmap.bit_pos;
58 *((unsigned *)mmap_reg) |= (1<<bitpos);
61 *((unsigned *)mmap_reg) &= ~(1<<bitpos);
67 mraa_intel_galileo_g1_mmap_setup(mraa_gpio_context dev, mraa_boolean_t en)
70 syslog(LOG_ERR, "galileo1: Gpio context not valid");
71 return MRAA_ERROR_INVALID_HANDLE;
74 if (mraa_pin_mode_test(dev->phy_pin, MRAA_PIN_FAST_GPIO) == 0) {
75 syslog(LOG_WARNING, "galileo1: Mmap not available on this pin");
76 return MRAA_ERROR_NO_RESOURCES;
79 if (dev->mmap_write == NULL) {
80 syslog(LOG_NOTICE, "galileo1: Can't disable disabled mmap gpio");
81 return MRAA_ERROR_INVALID_PARAMETER;
83 dev->mmap_write = NULL;
85 if (mmap_count == 0) {
86 return mraa_intel_galileo_g1_mmap_unsetup();
91 if (dev->mmap_write != NULL) {
92 syslog(LOG_ERR, "galileo1: Can't enable enabled mmap gpio");
93 return MRAA_ERROR_INVALID_PARAMETER;
95 if (mmap_reg == NULL) {
96 if ((mmap_fd = open(UIO_PATH, O_RDWR)) < 0) {
97 syslog(LOG_ERR, "galileo1: Unable to open UIO device");
98 return MRAA_ERROR_INVALID_RESOURCE;
100 mmap_reg = mmap(NULL, mmap_size, PROT_READ|PROT_WRITE,
101 MAP_SHARED, mmap_fd, 0);
103 if (mmap_reg == MAP_FAILED) {
104 syslog(LOG_ERR, "galileo1: Mmap failed to mmap");
107 return MRAA_ERROR_NO_RESOURCES;
110 if (mraa_setup_mux_mapped(plat->pins[dev->phy_pin].mmap.gpio)
112 syslog(LOG_ERR, "galileo1: Unable to setup required multiplexers for mmap");
113 return MRAA_ERROR_INVALID_RESOURCE;
115 dev->mmap_write = &mraa_intel_galileo_g1_mmap_write;
121 mraa_intel_galileo_rev_d()
123 mraa_board_t* b = (mraa_board_t*) malloc(sizeof(mraa_board_t));
128 b->platform_name = PLATFORM_NAME;
129 b->phy_pin_count = 20;
132 b->uart_dev_count = 2;
135 b->adc_supported = 10;
136 b->pwm_default_period = 500;
137 b->pwm_max_period = 7968;
138 b->pwm_min_period = 1;
140 advance_func->gpio_mmap_setup = &mraa_intel_galileo_g1_mmap_setup;
142 b->pins = (mraa_pininfo_t*) malloc(sizeof(mraa_pininfo_t)*MRAA_INTEL_GALILEO_REV_D_PINCOUNT);
143 if (b->pins == NULL) {
148 strncpy(b->pins[0].name, "IO0", 8);
149 b->pins[0].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
150 b->pins[0].gpio.pinmap = 50;
151 b->pins[0].gpio.parent_id = 0;
152 b->pins[0].gpio.mux_total = 1;
153 b->pins[0].gpio.mux[0].pin = 40;
154 b->pins[0].gpio.mux[0].value = 1;
155 b->pins[0].uart.pinmap = 0;
156 b->pins[0].uart.parent_id = 0;
157 b->pins[0].uart.mux_total = 1;
158 b->pins[0].uart.mux[0].pin = 40;
159 b->pins[0].uart.mux[0].value = 0;
161 strncpy(b->pins[1].name, "IO1", 8);
162 b->pins[1].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,1};
163 b->pins[1].gpio.pinmap = 51;
164 b->pins[1].gpio.mux_total = 1;
165 b->pins[1].gpio.mux[0].pin = 41;
166 b->pins[1].gpio.mux[0].value = 1;
167 b->pins[1].uart.pinmap = 0;
168 b->pins[1].uart.parent_id = 0;
169 b->pins[1].uart.mux_total = 1;
170 b->pins[1].uart.mux[0].pin = 41;
171 b->pins[1].uart.mux[0].value = 0;
173 strncpy(b->pins[2].name, "IO2", 8);
174 b->pins[2].capabilites = (mraa_pincapabilities_t) {1,1,0,1,0,0,0,0};
175 b->pins[2].gpio.pinmap = 32;
176 b->pins[2].gpio.mux_total = 1;
177 b->pins[2].gpio.mux[0].pin = 31;
178 b->pins[2].gpio.mux[0].value = 1;
179 b->pins[2].mmap.gpio.pinmap = 14;
180 strncpy(b->pins[2].mmap.mem_dev, "/dev/uio0", 12);
181 b->pins[2].mmap.gpio.mux_total = 2;
182 b->pins[2].mmap.gpio.mux[0].pin = 31;
183 b->pins[2].mmap.gpio.mux[0].value = 0;
184 b->pins[2].mmap.gpio.mux[1].pin = 14;
185 b->pins[2].mmap.gpio.mux[1].value = 0;
186 b->pins[2].mmap.mem_sz = 0x1000;
187 b->pins[2].mmap.bit_pos = 6;
189 strncpy(b->pins[3].name, "IO3", 8);
190 b->pins[3].capabilites = (mraa_pincapabilities_t) {1,1,1,1,0,0,0,0};
191 b->pins[3].gpio.pinmap = 18;
192 b->pins[3].gpio.mux_total = 1;
193 b->pins[3].gpio.mux[0].pin = 30;
194 b->pins[3].gpio.mux[0].value = 1;
195 b->pins[3].mmap.gpio.pinmap = 15;
196 strncpy(b->pins[3].mmap.mem_dev, "/dev/uio0", 12);
197 b->pins[3].mmap.gpio.mux_total = 2;
198 b->pins[3].mmap.gpio.mux[0].pin = 30;
199 b->pins[3].mmap.gpio.mux[0].value = 0;
200 b->pins[3].mmap.gpio.mux[1].pin = 15;
201 b->pins[3].mmap.gpio.mux[1].value = 0;
202 b->pins[3].mmap.mem_sz = 0x1000;
203 b->pins[3].mmap.bit_pos = 7;
204 b->pins[3].pwm.pinmap = 3;
205 b->pins[3].pwm.parent_id = 0;
206 b->pins[3].pwm.mux_total = 1;
207 b->pins[3].pwm.mux[0].pin = 30;
208 b->pins[3].pwm.mux[0].value = 1;
211 strncpy(b->pins[4].name, "IO4", 8);
212 b->pins[4].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
213 b->pins[4].gpio.pinmap = 28;
214 b->pins[4].gpio.mux_total = 0;
216 strncpy(b->pins[5].name, "IO5", 8);
217 b->pins[5].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
218 b->pins[5].gpio.pinmap = 17;
219 b->pins[5].gpio.mux_total = 0;
220 b->pins[5].pwm.pinmap = 5;
221 b->pins[5].pwm.parent_id = 0;
222 b->pins[5].pwm.mux_total = 0;
224 strncpy(b->pins[6].name, "IO6", 8);
225 b->pins[6].gpio.pinmap = 24;
226 b->pins[6].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
227 b->pins[6].gpio.mux_total = 0;
228 b->pins[6].pwm.pinmap = 6;
229 b->pins[6].pwm.parent_id = 0;
230 b->pins[6].pwm.mux_total = 0;
232 strncpy(b->pins[7].name, "IO7", 8);
233 b->pins[7].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
234 b->pins[7].gpio.pinmap = 27;
235 b->pins[7].gpio.mux_total = 0;
237 strncpy(b->pins[8].name, "IO8", 8);
238 b->pins[8].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,0,0};
239 b->pins[8].gpio.pinmap = 26;
240 b->pins[8].gpio.mux_total = 0;
242 strncpy(b->pins[9].name, "IO9", 8);
243 b->pins[9].capabilites = (mraa_pincapabilities_t) {1,1,1,0,0,0,0,0};
244 b->pins[9].gpio.pinmap = 19;
245 b->pins[9].gpio.mux_total = 0;
246 b->pins[9].pwm.pinmap = 1;
247 b->pins[9].pwm.parent_id = 0;
248 b->pins[9].pwm.mux_total = 0;
250 strncpy(b->pins[10].name, "IO10", 8);
251 b->pins[10].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0,0};
252 b->pins[10].gpio.pinmap = 16;
253 b->pins[10].gpio.mux_total = 1;
254 b->pins[10].gpio.mux[0].pin = 42;
255 b->pins[10].gpio.mux[0].value = 1;
256 b->pins[10].pwm.pinmap = 7;
257 b->pins[10].pwm.parent_id = 0;
258 b->pins[10].pwm.mux_total = 1;
259 b->pins[10].pwm.mux[0].pin = 42;
260 b->pins[10].pwm.mux[0].value = 1;
261 b->pins[10].spi.pinmap = 1;
262 b->pins[10].spi.mux_total = 1;
263 b->pins[10].spi.mux[0].pin = 42;
264 b->pins[10].spi.mux[0].value = 0;
266 strncpy(b->pins[11].name, "IO11", 8);
267 b->pins[11].capabilites = (mraa_pincapabilities_t) {1,1,1,0,1,0,0,0};
268 b->pins[11].gpio.pinmap = 25;
269 b->pins[11].gpio.mux_total = 1;
270 b->pins[11].gpio.mux[0].pin = 43;
271 b->pins[11].gpio.mux[0].value = 1;
272 b->pins[11].pwm.pinmap = 4;
273 b->pins[11].pwm.parent_id = 0;
274 b->pins[11].pwm.mux_total = 1;
275 b->pins[11].pwm.mux[0].pin = 43;
276 b->pins[11].pwm.mux[0].value = 1;
277 b->pins[11].spi.pinmap = 1;
278 b->pins[11].spi.mux_total = 1;
279 b->pins[11].spi.mux[0].pin = 43;
280 b->pins[11].spi.mux[0].value = 0;
282 strncpy(b->pins[12].name, "IO12", 8);
283 b->pins[12].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
284 b->pins[12].gpio.pinmap = 38;
285 b->pins[12].gpio.mux_total = 1;
286 b->pins[12].gpio.mux[0].pin = 54;
287 b->pins[12].gpio.mux[0].value = 1;
288 b->pins[12].spi.pinmap = 1;
289 b->pins[12].spi.mux_total = 1;
290 b->pins[12].spi.mux[0].pin = 54;
291 b->pins[12].spi.mux[0].value = 0;
293 strncpy(b->pins[13].name, "IO13", 8);
294 b->pins[13].capabilites = (mraa_pincapabilities_t) {1,1,0,0,1,0,0,0};
295 b->pins[13].gpio.pinmap = 39;
296 b->pins[13].gpio.mux_total = 1;
297 b->pins[13].gpio.mux[0].pin = 55;
298 b->pins[13].gpio.mux[0].value = 1;
299 b->pins[13].spi.pinmap = 1;
300 b->pins[13].spi.mux_total = 1;
301 b->pins[13].spi.mux[0].pin = 55;
302 b->pins[13].spi.mux[0].value = 0;
304 strncpy(b->pins[14].name, "A0", 8);
305 b->pins[14].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
306 b->pins[14].gpio.pinmap = 44;
307 b->pins[14].gpio.mux_total = 1;
308 b->pins[14].gpio.mux[0].pin = 37;
309 b->pins[14].gpio.mux[0].value = 1;
310 b->pins[14].aio.pinmap = 0;
311 b->pins[14].aio.mux_total = 1;
312 b->pins[14].aio.mux[0].pin = 37;
313 b->pins[14].aio.mux[0].value = 0;
315 strncpy(b->pins[15].name, "A1", 8);
316 b->pins[15].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
317 b->pins[15].gpio.pinmap = 45;
318 b->pins[15].gpio.mux_total = 1;
319 b->pins[15].gpio.mux[0].pin = 36;
320 b->pins[15].gpio.mux[0].value = 1;
321 b->pins[15].aio.pinmap = 1;
322 b->pins[15].aio.mux_total = 1;
323 b->pins[15].aio.mux[0].pin = 36;
324 b->pins[15].aio.mux[0].value = 0;
326 strncpy(b->pins[16].name, "A2", 8);
327 b->pins[16].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
328 b->pins[16].gpio.pinmap = 46;
329 b->pins[16].gpio.mux_total = 1;
330 b->pins[16].gpio.mux[0].pin = 23;
331 b->pins[16].gpio.mux[0].value = 1;
332 b->pins[16].aio.pinmap = 2;
333 b->pins[16].aio.mux_total = 1;
334 b->pins[16].aio.mux[0].pin = 23;
335 b->pins[16].aio.mux[0].value = 0;
337 strncpy(b->pins[17].name, "A3", 8);
338 b->pins[17].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,0,1,0};
339 b->pins[17].gpio.pinmap = 47;
340 b->pins[17].gpio.mux_total = 1;
341 b->pins[17].gpio.mux[0].pin = 22;
342 b->pins[17].gpio.mux[0].value = 1;
343 b->pins[17].aio.pinmap = 3;
344 b->pins[17].aio.mux_total = 1;
345 b->pins[17].aio.mux[0].pin = 22;
346 b->pins[17].aio.mux[0].value = 0;
348 strncpy(b->pins[18].name, "A4", 8);
349 b->pins[18].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
350 b->pins[18].gpio.pinmap = 48;
351 b->pins[18].gpio.mux_total = 2;
352 b->pins[18].gpio.mux[0].pin = 29;
353 b->pins[18].gpio.mux[0].value = 1;
354 b->pins[18].gpio.mux[1].pin = 21;
355 b->pins[18].gpio.mux[1].value = 1;
356 b->pins[18].i2c.pinmap = 1;
357 b->pins[18].i2c.mux_total = 1;
358 b->pins[18].i2c.mux[0].pin = 29;
359 b->pins[18].i2c.mux[0].value = 0;
360 b->pins[18].aio.pinmap = 4;
361 b->pins[18].aio.mux_total = 2;
362 b->pins[18].aio.mux[0].pin = 29;
363 b->pins[18].aio.mux[0].value = 1;
364 b->pins[18].aio.mux[1].pin = 21;
365 b->pins[18].aio.mux[1].value = 0;
367 strncpy(b->pins[19].name, "A5", 8);
368 b->pins[19].capabilites = (mraa_pincapabilities_t) {1,1,0,0,0,1,1,0};
369 b->pins[19].gpio.pinmap = 49;
370 b->pins[19].gpio.mux_total = 2;
371 b->pins[19].gpio.mux[0].pin = 29;
372 b->pins[19].gpio.mux[0].value = 1;
373 b->pins[19].gpio.mux[1].pin = 20;
374 b->pins[19].gpio.mux[1].value = 1;
375 b->pins[19].i2c.pinmap = 1;
376 b->pins[19].i2c.mux_total = 1;
377 b->pins[19].i2c.mux[0].pin = 29;
378 b->pins[19].i2c.mux[0].value = 0;
379 b->pins[19].aio.pinmap = 5;
380 b->pins[19].aio.mux_total = 2;
381 b->pins[19].aio.mux[0].pin = 29;
382 b->pins[19].aio.mux[0].value = 1;
383 b->pins[19].aio.mux[1].pin = 20;
384 b->pins[19].aio.mux[1].value = 0;
387 b->i2c_bus_count = 1;
389 b->i2c_bus[0].bus_id = 0;
390 b->i2c_bus[0].sda = 18;
391 b->i2c_bus[0].scl = 19;
393 b->spi_bus_count = 1;
395 b->spi_bus[0].bus_id = 1;
396 b->spi_bus[0].slave_s = 0;
397 b->spi_bus[0].cs = 10;
398 b->spi_bus[0].mosi = 11;
399 b->spi_bus[0].miso = 12;
400 b->spi_bus[0].sclk = 13;
402 b->uart_dev_count = 2;
404 b->uart_dev[0].rx = 0;
405 b->uart_dev[0].tx = 1;
406 b->uart_dev[0].device_path = "/dev/ttyS0";
408 b->uart_dev[1].rx = -1;
409 b->uart_dev[1].tx = -1;
410 b->uart_dev[1].device_path = "/dev/ttyS1";
414 syslog(LOG_CRIT, "galileo1: Platform failed to initialise");