Revert "BDW: Change the default tiling mode to TILING_Y on BDW."

This reverts commit f2c57a46de4f51fa5d4c8e02cc751fce7ff417c8.

diff --git a/src/cl_mem.c b/src/cl_mem.c
index 100545d..0fbd304 100644 (file)
--- a/src/cl_mem.c
+++ b/src/cl_mem.c
@@ -637,14 +637,10 @@ cl_mem_copy_image(struct _cl_mem_image *image,
   cl_mem_unmap_auto((cl_mem)image);
 }
 
-cl_image_tiling_t cl_get_default_tiling(cl_driver drv)
+cl_image_tiling_t cl_get_default_tiling(void)
 {
   static int initialized = 0;
-  cl_image_tiling_t tiling = CL_TILE_X;
-
-  // FIXME, need to find out the performance diff's root cause on BDW.
-  if(cl_driver_get_ver(drv) == 8)
-    tiling = CL_TILE_Y;
+  static cl_image_tiling_t tiling = CL_TILE_X;
   if (!initialized) {
     char *tilingStr = getenv("OCL_TILING");
     if (tilingStr != NULL) {
@@ -737,7 +733,7 @@ _cl_mem_new_image(cl_context ctx,
 
     /* Pick up tiling mode (we do only linear on SNB) */
     if (cl_driver_get_ver(ctx->drv) != 6)
-      tiling = cl_get_default_tiling(ctx->drv);
+      tiling = cl_get_default_tiling();
 
     depth = 1;
   } else if (image_type == CL_MEM_OBJECT_IMAGE3D ||
@@ -747,7 +743,7 @@ _cl_mem_new_image(cl_context ctx,
       h = 1;
       tiling = CL_NO_TILE;
     } else if (cl_driver_get_ver(ctx->drv) != 6)
-      tiling = cl_get_default_tiling(ctx->drv);
+      tiling = cl_get_default_tiling();
 
     size_t min_pitch = bpp * w;
     if (data && pitch == 0)