2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
31 abi16_chan_nv04(struct nouveau_object *obj)
33 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
34 struct nv04_fifo *nv04 = obj->data;
35 struct drm_nouveau_channel_alloc req = {nv04->vram, nv04->gart};
38 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
43 nv04->base.channel = req.channel;
44 nv04->base.pushbuf = req.pushbuf_domains;
45 nv04->notify = req.notifier_handle;
46 nv04->base.object->handle = req.channel;
47 nv04->base.object->length = sizeof(*nv04);
52 abi16_chan_nvc0(struct nouveau_object *obj)
54 struct nouveau_device *dev = (struct nouveau_device *)obj->parent;
55 struct drm_nouveau_channel_alloc req = {};
56 struct nvc0_fifo *nvc0 = obj->data;
59 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_CHANNEL_ALLOC,
64 nvc0->base.channel = req.channel;
65 nvc0->base.pushbuf = req.pushbuf_domains;
66 nvc0->notify = req.notifier_handle;
67 nvc0->base.object->handle = req.channel;
68 nvc0->base.object->length = sizeof(*nvc0);
73 abi16_engobj(struct nouveau_object *obj)
75 struct drm_nouveau_grobj_alloc req = {
76 obj->parent->handle, obj->handle, obj->oclass
78 struct nouveau_device *dev;
81 dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
82 ret = drmCommandWrite(dev->fd, DRM_NOUVEAU_GROBJ_ALLOC,
87 obj->length = sizeof(struct nouveau_object *);
92 abi16_ntfy(struct nouveau_object *obj)
94 struct nv04_notify *ntfy = obj->data;
95 struct drm_nouveau_notifierobj_alloc req = {
96 obj->parent->handle, ntfy->object->handle, ntfy->length
98 struct nouveau_device *dev;
101 dev = nouveau_object_find(obj, NOUVEAU_DEVICE_CLASS);
102 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_NOTIFIEROBJ_ALLOC,
107 ntfy->offset = req.offset;
108 ntfy->object->length = sizeof(*ntfy);
113 abi16_bo_info(struct nouveau_bo *bo, struct drm_nouveau_gem_info *info)
115 struct nouveau_bo_priv *nvbo = nouveau_bo(bo);
117 nvbo->map_handle = info->map_handle;
118 bo->handle = info->handle;
119 bo->size = info->size;
120 bo->offset = info->offset;
123 if (info->domain & NOUVEAU_GEM_DOMAIN_VRAM)
124 bo->flags |= NOUVEAU_BO_VRAM;
125 if (info->domain & NOUVEAU_GEM_DOMAIN_GART)
126 bo->flags |= NOUVEAU_BO_GART;
127 if (!(info->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG))
128 bo->flags |= NOUVEAU_BO_CONTIG;
129 if (nvbo->map_handle)
130 bo->flags |= NOUVEAU_BO_MAP;
132 if (bo->device->chipset >= 0xc0) {
133 bo->config.nvc0.memtype = (info->tile_flags & 0xff00) >> 8;
134 bo->config.nvc0.tile_mode = info->tile_mode;
136 if (bo->device->chipset >= 0x80 || bo->device->chipset == 0x50) {
137 bo->config.nv50.memtype = (info->tile_flags & 0x07f00) >> 8 |
138 (info->tile_flags & 0x30000) >> 9;
139 bo->config.nv50.tile_mode = info->tile_mode << 4;
141 bo->config.nv04.surf_flags = info->tile_flags & 7;
142 bo->config.nv04.surf_pitch = info->tile_mode;
147 abi16_bo_init(struct nouveau_bo *bo, uint32_t alignment,
148 union nouveau_bo_config *config)
150 struct nouveau_device *dev = bo->device;
151 struct drm_nouveau_gem_new req = {};
152 struct drm_nouveau_gem_info *info = &req.info;
155 if (bo->flags & NOUVEAU_BO_VRAM)
156 info->domain |= NOUVEAU_GEM_DOMAIN_VRAM;
157 if (bo->flags & NOUVEAU_BO_GART)
158 info->domain |= NOUVEAU_GEM_DOMAIN_GART;
160 info->domain |= NOUVEAU_GEM_DOMAIN_VRAM |
161 NOUVEAU_GEM_DOMAIN_GART;
163 if (bo->flags & NOUVEAU_BO_MAP)
164 info->domain |= NOUVEAU_GEM_DOMAIN_MAPPABLE;
166 if (!(bo->flags & NOUVEAU_BO_CONTIG))
167 info->tile_flags = NOUVEAU_GEM_TILE_NONCONTIG;
169 info->size = bo->size;
170 req.align = alignment;
173 if (dev->chipset >= 0xc0) {
174 info->tile_flags = (config->nvc0.memtype & 0xff) << 8;
175 info->tile_mode = config->nvc0.tile_mode;
177 if (dev->chipset >= 0x80 || dev->chipset == 0x50) {
178 info->tile_flags = (config->nv50.memtype & 0x07f) << 8 |
179 (config->nv50.memtype & 0x180) << 9;
180 info->tile_mode = config->nv50.tile_mode >> 4;
182 info->tile_flags = config->nv04.surf_flags & 7;
183 info->tile_mode = config->nv04.surf_pitch;
187 if (!nouveau_device(dev)->have_bo_usage)
188 info->tile_flags &= 0x0000ff00;
190 ret = drmCommandWriteRead(dev->fd, DRM_NOUVEAU_GEM_NEW,
193 abi16_bo_info(bo, &req.info);