intel/intel_chipset.h

   1 /*
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 #ifndef _INTEL_CHIPSET_H
  29 #define _INTEL_CHIPSET_H
  30
  31 #define PCI_CHIP_ILD_G                  0x0042
  32 #define PCI_CHIP_ILM_G                  0x0046
  33
  34 #define PCI_CHIP_SANDYBRIDGE_GT1        0x0102 /* desktop */
  35 #define PCI_CHIP_SANDYBRIDGE_GT2        0x0112
  36 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS   0x0122
  37 #define PCI_CHIP_SANDYBRIDGE_M_GT1      0x0106 /* mobile */
  38 #define PCI_CHIP_SANDYBRIDGE_M_GT2      0x0116
  39 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
  40 #define PCI_CHIP_SANDYBRIDGE_S          0x010A /* server */
  41
  42 #define PCI_CHIP_IVYBRIDGE_GT1          0x0152 /* desktop */
  43 #define PCI_CHIP_IVYBRIDGE_GT2          0x0162
  44 #define PCI_CHIP_IVYBRIDGE_M_GT1        0x0156 /* mobile */
  45 #define PCI_CHIP_IVYBRIDGE_M_GT2        0x0166
  46 #define PCI_CHIP_IVYBRIDGE_S            0x015a /* server */
  47 #define PCI_CHIP_IVYBRIDGE_S_GT2        0x016a /* server */
  48
  49 #define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
  50 #define PCI_CHIP_HASWELL_GT2            0x0412
  51 #define PCI_CHIP_HASWELL_GT2_PLUS       0x0422
  52 #define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
  53 #define PCI_CHIP_HASWELL_M_GT2          0x0416
  54 #define PCI_CHIP_HASWELL_M_GT2_PLUS     0x0426
  55 #define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
  56 #define PCI_CHIP_HASWELL_S_GT2          0x041A
  57 #define PCI_CHIP_HASWELL_S_GT2_PLUS     0x042A
  58 #define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
  59 #define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
  60 #define PCI_CHIP_HASWELL_SDV_GT2_PLUS   0x0C22
  61 #define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
  62 #define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
  63 #define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
  64 #define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
  65 #define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
  66 #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
  67 #define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
  68 #define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
  69 #define PCI_CHIP_HASWELL_ULT_GT2_PLUS   0x0A22
  70 #define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
  71 #define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
  72 #define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
  73 #define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
  74 #define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
  75 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
  76 #define PCI_CHIP_HASWELL_CRW_GT1        0x0D12 /* Desktop */
  77 #define PCI_CHIP_HASWELL_CRW_GT2        0x0D22
  78 #define PCI_CHIP_HASWELL_CRW_GT2_PLUS   0x0D32
  79 #define PCI_CHIP_HASWELL_CRW_M_GT1      0x0D16 /* Mobile */
  80 #define PCI_CHIP_HASWELL_CRW_M_GT2      0x0D26
  81 #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
  82 #define PCI_CHIP_HASWELL_CRW_S_GT1      0x0D1A /* Server */
  83 #define PCI_CHIP_HASWELL_CRW_S_GT2      0x0D2A
  84 #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
  85
  86 #define IS_830(dev) (dev == 0x3577)
  87 #define IS_845(dev) (dev == 0x2562)
  88 #define IS_85X(dev) (dev == 0x3582)
  89 #define IS_865(dev) (dev == 0x2572)
  90
  91 #define IS_GEN2(dev) (IS_830(dev) ||                            \
  92                       IS_845(dev) ||                            \
  93                       IS_85X(dev) ||                            \
  94                       IS_865(dev))
  95
  96 #define IS_915G(dev) (dev == 0x2582 ||          \
  97                        dev == 0x258a)
  98 #define IS_915GM(dev) (dev == 0x2592)
  99 #define IS_945G(dev) (dev == 0x2772)
 100 #define IS_945GM(dev) (dev == 0x27A2 ||         \
 101                         dev == 0x27AE)
 102
 103 #define IS_915(dev) (IS_915G(dev) ||                            \
 104                      IS_915GM(dev))
 105
 106 #define IS_945(dev) (IS_945G(dev) ||                            \
 107                      IS_945GM(dev) ||                           \
 108                      IS_G33(dev) ||                             \
 109                      IS_PINEVIEW(dev))
 110
 111 #define IS_G33(dev)    (dev == 0x29C2 ||                \
 112                         dev == 0x29B2 ||                \
 113                         dev == 0x29D2)
 114
 115 #define IS_PINEVIEW(dev) (dev == 0xa001 ||      \
 116                           dev == 0xa011)
 117
 118 #define IS_GEN3(dev) (IS_915(dev) ||                            \
 119                       IS_945(dev) ||                            \
 120                       IS_G33(dev) ||                            \
 121                       IS_PINEVIEW(dev))
 122
 123 #define IS_I965GM(dev) (dev == 0x2A02)
 124
 125 #define IS_GEN4(dev) (dev == 0x2972 ||  \
 126                       dev == 0x2982 ||  \
 127                       dev == 0x2992 ||  \
 128                       dev == 0x29A2 ||  \
 129                       dev == 0x2A02 ||  \
 130                       dev == 0x2A12 ||  \
 131                       dev == 0x2A42 ||  \
 132                       dev == 0x2E02 ||  \
 133                       dev == 0x2E12 ||  \
 134                       dev == 0x2E22 ||  \
 135                       dev == 0x2E32 ||  \
 136                       dev == 0x2E42 ||  \
 137                       dev == 0x0042 ||  \
 138                       dev == 0x0046 ||  \
 139                       IS_I965GM(dev) || \
 140                       IS_G4X(dev))
 141
 142 #define IS_GM45(dev) (dev == 0x2A42)
 143
 144
 145 #define IS_GEN5(dev)    (dev == PCI_CHIP_ILD_G || \
 146                          dev == PCI_CHIP_ILM_G)
 147
 148 #define IS_GEN6(dev)    (dev == PCI_CHIP_SANDYBRIDGE_GT1 || \
 149                          dev == PCI_CHIP_SANDYBRIDGE_GT2 || \
 150                          dev == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
 151                          dev == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
 152                          dev == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
 153                          dev == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
 154                          dev == PCI_CHIP_SANDYBRIDGE_S)
 155
 156 #define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
 157                                  IS_HASWELL(devid))
 158
 159 #define IS_IVYBRIDGE(dev)       (dev == PCI_CHIP_IVYBRIDGE_GT1 || \
 160                                  dev == PCI_CHIP_IVYBRIDGE_GT2 || \
 161                                  dev == PCI_CHIP_IVYBRIDGE_M_GT1 || \
 162                                  dev == PCI_CHIP_IVYBRIDGE_M_GT2 || \
 163                                  dev == PCI_CHIP_IVYBRIDGE_S || \
 164                                  dev == PCI_CHIP_IVYBRIDGE_S_GT2)
 165
 166 #define IS_HSW_GT1(devid)       (devid == PCI_CHIP_HASWELL_GT1 || \
 167                                  devid == PCI_CHIP_HASWELL_M_GT1 || \
 168                                  devid == PCI_CHIP_HASWELL_S_GT1 || \
 169                                  devid == PCI_CHIP_HASWELL_SDV_GT1 || \
 170                                  devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
 171                                  devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
 172                                  devid == PCI_CHIP_HASWELL_ULT_GT1 || \
 173                                  devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
 174                                  devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
 175                                  devid == PCI_CHIP_HASWELL_CRW_GT1 || \
 176                                  devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
 177                                  devid == PCI_CHIP_HASWELL_CRW_S_GT1)
 178 #define IS_HSW_GT2(devid)       (devid == PCI_CHIP_HASWELL_GT2 || \
 179                                  devid == PCI_CHIP_HASWELL_M_GT2 || \
 180                                  devid == PCI_CHIP_HASWELL_S_GT2 || \
 181                                  devid == PCI_CHIP_HASWELL_SDV_GT2 || \
 182                                  devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \
 183                                  devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \
 184                                  devid == PCI_CHIP_HASWELL_ULT_GT2 || \
 185                                  devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \
 186                                  devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \
 187                                  devid == PCI_CHIP_HASWELL_CRW_GT2 || \
 188                                  devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \
 189                                  devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \
 190                                  devid == PCI_CHIP_HASWELL_GT2_PLUS || \
 191                                  devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \
 192                                  devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \
 193                                  devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
 194                                  devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
 195                                  devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
 196                                  devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
 197                                  devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
 198                                  devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
 199                                  devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
 200                                  devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
 201                                  devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
 202
 203 #define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
 204                                  IS_HSW_GT2(devid))
 205
 206 #define IS_G4X(dev) (dev == 0x2E02 || \
 207                      dev == 0x2E12 || \
 208                      dev == 0x2E22 || \
 209                      dev == 0x2E32 || \
 210                      dev == 0x2E42 || \
 211                      IS_GM45(dev))
 212
 213 #define IS_9XX(dev) (IS_GEN3(dev) ||                            \
 214                      IS_GEN4(dev) ||                            \
 215                      IS_GEN5(dev) ||                            \
 216                      IS_GEN6(dev) ||                            \
 217                      IS_GEN7(dev))
 218
 219 #endif /* _INTEL_CHIPSET_H */