subpicture: don't overallocate palette on 64-bit systems.

Allocate the exact amount of memory for VA image palettes on 64-bit
systems. No more.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

subpicture: fix creation of IA88/AI88 subpicture images.

IA88 format is 16bpp, with one byte for alpha and one byte for the color
index. Besides, a palette with 256 entries is also needed.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

subpicture: expose "global-alpha" is supported.

Make sure vaQuerySubpictureFormats() reports that "global-alpha" is
supported, along with "screen-coords".

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

subpicture: don't overallocate palette on 64-bit systems.

Allocate the exact amount of memory for VA image palettes on 64-bit
systems. No more.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

subpicture: fix creation of IA88/AI88 subpicture images.

IA88 format is 16bpp, with one byte for alpha and one byte for the color
index. Besides, a palette with 256 entries is also needed.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

subpicture: expose "global-alpha" is supported.

Make sure vaQuerySubpictureFormats() reports that "global-alpha" is
supported, along with "screen-coords".

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Render: Update the maximum number of WM threads

The number is stolen from Mesa.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: zaverel <zaverel@free.fr>
(cherry picked from commit a140c632046e50a41bf75da097834fd9954b9561)

Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_HSW_GT2_PLUS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit bb946b7d2c97c94ac1888195ab1d5b9c59750d23)

Adopt the same fix used in the commit 29d73dc to HSW

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

h264: fix first macroblock bit offset calculation (ILK, SNB, IVB).

Fix and simplify the scan for emulation_prevention_bytes, thus avoiding
a read beyond the end of the slice data buffer. Besides, if slice_header()
bytes are needed, use dri_bo_get_subdata() instead.

HW specific changes:
- SNB: make the HW skip the emulation prevention bytes itself.
- IVB: fix MFD_AVC_BSD_OBJECT to report the actual slice data buffer size.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit 9b7863bf49dcf8bf1de9b45ce4e986dfd1cca418)

Render: Update the maximum number of WM threads

The number is stolen from Mesa.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57323
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: zaverel <zaverel@free.fr>

Add IS_SNB_GT1/IS_SNB_GT2/IS_IVB_GT1/IS_IVB_GT2 and remove IS_HSW_ULT and IS_HSW_GT2_PLUS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix the compile error in the previous commit

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: fix the AVS steping and frame origin issue

On HSW/IVB, when the resolution of source rectangle is
not the same as src surface, or the source rectangle does
not locate at (0,0), the scaled picture is not correct,
adjust the steping size and frame origin according to the
src rectangle's location and resolution.

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

workaround to set VC1 overlap filter flag

Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>

Fill the bitplane for VC1 skip picture decoding

This is a workaround for VC1 skip picture, the corresponding
bit value in bitplane should be 1 for skip picture, but sometimes
application pass down wrong value.

Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>

MPEG-2 encoding on Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

MPEG-2 encoding path

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix Motion Vector

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

MPEG-2 encoding: Use pre deblocking output for reconstructed picture.

This avoids OLDB enabling for MPEG-2

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fixed an assertion failure

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Follow the vme output to configure PAK command

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Shader for MPEG-2 encoding

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix the number of MVs for MPEG-2 encoding

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

PAK command for inter macroblock

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

vme for MPEG-2 on Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

New field profile in struct intel_encoder_context

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

gen75_vme.c: Fix some indentation

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Update coded_block_pattern

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Change the max size

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Update QM/FQM matrices for MPEG-2 encoding

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

No emulation bytes for MPEG-2

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Internal flag for the coded buffer

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

rename I965_CODEDBUFFER_SIZE

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Insert some redunrant data around a slice

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Setup MFC pipeline for MPEG-2 encoding on Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Explicitly clarify features

Also simplify some MACROs

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix H264 YUV400 surface render issue

All decoded frame are considered as NV12 format in driver's,
for YUV400 format senerios, we need set the chroma component
of NV12 to a constant value(0x80), otherwise the converted ARGB
from NV12 format is not correct and cause render issue.

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit 3ac4256d3aba3db757d086a7e7496d95cd8b0da4)

VPP: Add video sharpening processing feature on HSW

Video sharpening feature is implemented based on media
shared function pipeline, Y component of NV12 surface
will be sharpened.

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>

Fix H264 YUV400 surface render issue

All decoded frame are considered as NV12 format in driver's,
for YUV400 format senerios, we need set the chroma component
of NV12 to a constant value(0x80), otherwise the converted ARGB
from NV12 format is not correct and cause render issue.

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>

vc1: fix bitplane buffer size(HSW)

This fixes buffer overflow in the newly allocated Gen buffer
that holds VC-1 bitplanes.

Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>

vc1: fix bitplane buffer size (SNB, IVB).

This fixes buffer overflow in the newly allocated Gen buffer that holds
VC-1 bitplanes.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Render: Add four subpicture support

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit a7c42530c312bdb1c53cce49b6a86f47de2ccb65)

Conflicts:

src/i965_drv_video.c

Render: Add AI88/IA88 surface foramt support for subpicture

Signed off by: Li,Xiaowei A <xiaowei.a.li@intel.com>
(cherry picked from commit 6a641d0feda6ded2abcd907c4ceb5a45f134990d)

Conflicts:

src/i965_drv_video.h

Render: Add global alpha support for subpicture

Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>
(cherry picked from commit 06998b16f470ba49c2af0372e2ef7fee74b1d5b6)

Render: Add four subpicture support

Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>

Render: Add AI88/IA88 surface foramt support for subpicture

Signed off by: Li,Xiaowei A <xiaowei.a.li@intel.com>

Render: Add global alpha support for subpicture

Signed-off-by: Li Xiaowei A <xiaowei.a.li@intel.com>

Feed MFC PAK with correct MV of VME output on haswell

This is helpful to improve the video compress rate of H264 encoding.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Adjust the mode/mv cost for VME parameter based on QP for HSW

Currently it will use the same mode/mv cost regardless of QP during VME
prediction, which causes that we get the same VME prediction. It is better
that we get the different VME prediction mode based on QP, which can be
adopted by using mode/mv cost.
Now it is only applied on HSW.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the support of the chroma intra prediction on Haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the corrupted macroblock for AVC encoding on HSW

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add CSC conversion between RGBX and NV12 for HSW by using AVS shader

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Optimize the sampler 8x8 coefficients for AVS shader

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add the csc conversion from RGBX to NV12 on Ivy

It also applies when the source type is BGRX.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Add CSC conversion from NV12 to RGBX for VPP on Ivy

It also applies to the conversion from NV12 to BGRX.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

configure: add missing dependency to libm.

Build broke when trying to compile with expressive debug CFLAGS (-g3).
This was root-caused to the lack of the "-lm" linker flag. By adding a
simple autoconf check we ensure that libm is linked.

More specifically, recent VEBOX changes depend on cos() and sin() math
functions.

Signed-off-by: Joe Konno <joe.konno@intel.com>
(cherry picked from commit eb39abb70886d9277cf7d5114125cb7b22e7c362)

configure: add missing dependency to libm.

Build broke when trying to compile with expressive debug CFLAGS (-g3).
This was root-caused to the lack of the "-lm" linker flag. By adding a
simple autoconf check we ensure that libm is linked.

More specifically, recent VEBOX changes depend on cos() and sin() math
functions.

Signed-off-by: Joe Konno <joe.konno@intel.com>

wayland: port to 1.0 protocol.

Previously some of the functions that this code relied upon were exported as
symbols from the wayland-client .so. However those are now autogenerated
instead and are thus included as static inlines in the header file. Therefore
we must recreated the desired functions using the function pointers found in
the vtable.

Also following the removal of the globals hash from the client code it is
necessary to setup a registry with a listener on it to receive the global
objects.

Signed-off-by: Rob Bradford <rob@linux.intel.com>
(cherry picked from commit 63db874e9c924f086bcd3518cc0f3d8c6df9ecec)

wayland: port to 1.0 protocol.

Previously some of the functions that this code relied upon were exported as
symbols from the wayland-client .so. However those are now autogenerated
instead and are thus included as static inlines in the header file. Therefore
we must recreated the desired functions using the function pointers found in
the vtable.

Also following the removal of the globals hash from the client code it is
necessary to setup a registry with a listener on it to receive the global
objects.

Signed-off-by: Rob Bradford <rob@linux.intel.com>

Bump new version for development

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

intel driver  1.0.19

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Fix build and remaining compilation warnings.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

NEWS: minor wording fixes.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

Update NEWS

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Warning fixes

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Encoding: use a separated command buffer

The command buffer is adaptive to the size of the frame.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Add two helper functions for batchbuffer

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit 695c0b25d4f77d0b443ec97cfcb42f59b4df7e71)

Encoding: modify function to fill command into a specified batch buffer

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Allow to create batchbuffer based on the expected buffer size

This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch
buffer size can't hold the encoding command for 4Kx4K encoding.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Remove the hard coded value to suppor the 4Kx4K encoding

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the issue in i965_UnlockSurface to lock it next time

It uses the variable of locked_image_id to check whether one surface is locked
or not. But as the locked_image_id is not assigned correctly, it causes that
it can't lock one surface next time although it calls the vaUnlockSurfaces.
Then the libva trace log can't dump the content of decoded/
encoded surface even after adding LIBVA_TRACE_SURFACE=XXX.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Gwenole Beauchesne <gb.devel@gmail.com>

Avoid the dup of gen_free_avc_surface during compile

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Restrict the max MV number in MV prediction

This is to follow the level limits for MV number for the two
consecutive MBs in H264 Spec.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Allow to create batchbuffer based on the expected buffer size

This is to support the 4Kx4K encoding on Haswell. Otherwise the default batch
buffer size can't hold the encoding command for 4Kx4K encoding.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Remove the dup code of XXX_mfc_avc_prepare

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Remove the hard coded value to suppor the 4Kx4K encoding

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix the issue in i965_UnlockSurface to lock it next time

It uses the variable of locked_image_id to check whether one surface is locked
or not. But as the locked_image_id is not assigned correctly, it causes that
it can't lock one surface next time although it calls the vaUnlockSurfaces.
Then the libva trace log can't dump the content of decoded/
encoded surface even after adding LIBVA_TRACE_SURFACE=XXX.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Gwenole Beauchesne <gb.devel@gmail.com>

Unify the XXX_free_avc_surface for media encoding/decoding

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>

Fix thread issue with AVC private surafce

https://bugs.freedesktop.org/show_bug.cgi?id=55282

Signed-off-by: Gautam <manamgautam@gmail.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

Unify the code for xxx_free_avc_surface

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: refine code to resolve building warnings

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: add vebox context init and deinit

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: Alloc I965 batch buffer before initialization

VPP: Fix the surface flags and type setting

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: fix the usage of pp_static_parameter

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: work around hw limitation(dword alignment)

work around for horizontal offset on dst surface
left edge for load/save procedure

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Remove useless shader and refine shader list

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>

VPP: CSC on Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Build VPP shaders for Haswell

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: haswell: fix video post-processing setup.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>

VPP: The block mask workaround is only available for Sandy bridge

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP:work around hw limitation(dword alignment)

work around for horizontal offset on dst surface left edge for nv12 scaling (not avs)

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: work around hw limitation(dword alignment)

work around for horizontal offset on dst surface left edge (nv12 avs)

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>

VPP: Enable horizontal and vertical mask for bottom/right boundary blocks

Signed-off-by: Zhao,Halley <halley.zhao@intel.com>
- usually it is 0xff/0xffff for common blocks in grf5
- one mask is setup in object_walker when the last group of blocks are met
- another mask should setup when the last block (in a group) is met.
  it will be done in asm code, we make it ready in grf6

VPP: Adjust vertical scaling step for AVS on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: AVS workaround on IVB

Update AVS shaders and add CURBE parameters for AVS workaround

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Update the shader for DI on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: Add support DN on IVB

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>

VPP: New combined shaders for Ivybridge

In addtion, add the license header.

You need the latest intel-gen4asm to build these shaders

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>