andy.hu [Fri, 10 Feb 2023 07:49:36 +0000 (07:49 +0000)]
Merge branch 'CR_3317_qspi_compilation_into_ko_resume_exception' into 'jh7110-5.15.y-devel'
CR_3317_qspi_compilation_into_ko_resume_exception
See merge request sdk/linux!686
andy.hu [Fri, 10 Feb 2023 07:48:23 +0000 (07:48 +0000)]
Merge branch 'CR_3318_watchdog_compilation_into_ko_resume_exception' into 'jh7110-5.15.y-devel'
CR_3318_watchdog_compilation_into_ko_resume_exception
See merge request sdk/linux!690
ziv.xu [Thu, 9 Feb 2023 13:49:17 +0000 (21:49 +0800)]
starfive-wdt: add reset before resume
add reset before resume
Signed-off-by: ziv.xu <ziv.xu@starfive.com>
ziv.xu [Thu, 9 Feb 2023 02:15:59 +0000 (10:15 +0800)]
spi-cadence-quadspi: add reset before resume
add reset before resume
Signed-off-by: ziv.xu <ziv.xu@starfive.com>
andy.hu [Fri, 3 Feb 2023 11:55:11 +0000 (11:55 +0000)]
Merge branch 'CR_2975_5.15_hdmi_shengyang.chen' into 'jh7110-5.15.y-devel'
CR_2975_riscv: linux: vout: fix hdmi hibernation resume failure cause by pmic
See merge request sdk/linux!673
andy.hu [Fri, 3 Feb 2023 11:54:20 +0000 (11:54 +0000)]
Merge branch 'CR_3158_ISP_515_Kevin.xie' into 'jh7110-5.15.y-devel'
CR_3158: v4l2_driver: isp: Save & resore context regs during stream on/off.
See merge request sdk/linux!678
andy.hu [Fri, 3 Feb 2023 11:53:03 +0000 (11:53 +0000)]
Merge branch 'CR_3151_TDM_Hibernation_walker.chen' into 'jh7110-5.15.y-devel'
CR_3151_TDM_Hibernation_walker.chen
See merge request sdk/linux!682
andy.hu [Fri, 3 Feb 2023 11:51:36 +0000 (11:51 +0000)]
Merge branch 'CR_3137_usb_hiber_notify_minda' into 'jh7110-5.15.y-devel'
CR_3137 usb: cdns3: add hibernation pm notifier to set roothub wakeup
See merge request sdk/linux!679
andy.hu [Fri, 3 Feb 2023 11:35:13 +0000 (11:35 +0000)]
Merge branch 'CR_3170_spi_compiled_as_module_5.15_ziv.xu' into 'jh7110-5.15.y-devel'
CR_3170: spi-pl022-starfive:Enable spi to be compiled into modules
See merge request sdk/linux!677
andy.hu [Fri, 3 Feb 2023 11:30:19 +0000 (11:30 +0000)]
Merge branch 'CR_3231_515_PWMDAC_module_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_3231_515_PWMDAC_module_Xingyu.Wu
See merge request sdk/linux!680
andy.hu [Fri, 3 Feb 2023 11:29:02 +0000 (11:29 +0000)]
Merge branch 'CR_3157_imx219_515_changhuang.liang' into 'jh7110-5.15.y-devel'
CR_3157_imx219_515_changhuang.liang media: starfive: Modify support imx219 compile to module
See merge request sdk/linux!675
andy.hu [Fri, 3 Feb 2023 11:24:44 +0000 (11:24 +0000)]
Merge branch 'CR_2339_usb_read_using_sysport_minda' into 'jh7110-5.15.y-devel'
CR 2339 usb: xhci: To improve performance, using sysport for bulk read.
See merge request sdk/linux!590
Walker Chen [Fri, 3 Feb 2023 06:38:22 +0000 (14:38 +0800)]
CR_3151_TDM_Hibernation_walker.chen
Resolved the error of reording and playing simultaneously after performing
hibernation resume.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
minda.chen [Mon, 30 Jan 2023 09:12:36 +0000 (01:12 -0800)]
usb: cdns3: add hibernation pm notifier to set roothub wakeup
In hibernation resume case. usb devices maybe not emulated,
roothub is suspended, In this case, usb devices will be resume
fail. Set roothub active while hibernation resume.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
Xingyu Wu [Wed, 1 Feb 2023 03:18:38 +0000 (11:18 +0800)]
sound: starfive: pwmdac: Support module building
Change Makefile and Kconfig to support module building.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Kevin.xie [Mon, 30 Jan 2023 07:25:56 +0000 (15:25 +0800)]
v4l2_driver: isp: Save & resore context regs during stream on/off.
Besides, add some log in dump reg function to distinguish different groups.
Signed-off-by: Kevin.xie <kevin.xie@starfivetech.com>
shengyang.chen [Mon, 16 Jan 2023 11:45:28 +0000 (19:45 +0800)]
riscv: linux: vout: fix hdmi hibernation resume failure cause by pmic
fix hdmi hibernation resume failure cause by pmic
Signed-off-by: shengyang.chen<shengyang.chen@starfivetech.com>
minda.chen [Tue, 18 Oct 2022 01:57:39 +0000 (09:57 +0800)]
usb:xhci:To improve performance,usb using lowmem for bulk xfer.
Generate an usb low memory pool for usb 3.0 host
read/write transfer, default size is 8M.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
ziv.xu [Wed, 18 Jan 2023 07:50:47 +0000 (15:50 +0800)]
spi-pl022-starfive:Enable spi to be compiled into modules
Enable spi to be compiled into modules
Signed-off-by: ziv.xu <ziv.xu@starfive.com>
andy.hu [Wed, 18 Jan 2023 02:08:27 +0000 (02:08 +0000)]
Merge branch 'CR_3149_TempSensor_hal.feng' into 'jh7110-5.15.y-devel'
CR 3149 TempSensor hal.feng
See merge request sdk/linux!676
Samin Guo [Thu, 12 Jan 2023 04:53:02 +0000 (12:53 +0800)]
hwmon: sfctemp: Fix the problem that cannot disable sfctemp after enabling PM
[runtime_pm off]
After Linux starts, it will enable clk and put tempsensor in standby state.
When 'cat /sys/class/hwmon/hwmon0/temp1_input' is executed, will switch to
the run state, and return the value of the sensor after the interrupt is
generated.
$ cat /sys/kernel/debug/clk/clk_summary | grep "temp_sensor"
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------
u0_temp_sensor_clk_temp 1 1 0 1000000 0 0 50000 Y
u0_temp_sensor_clk_apb0 1 1 0
49500000 0 0 50000 Y
$ cat /sys/class/hwmon/hwmon0/temp1_input
46135
$ cat /sys/class/hwmon/hwmon0/temp1_enable
1
You can 'echo 0 >/sys/class/hwmon/hwmon0/temp1_enable' to turn off the
tempsensor and clk.
$ echo 0 > /sys/class/hwmon/hwmon0/temp1_enable
$ cat /sys/kernel/debug/clk/clk_summary | grep "temp_sensor"
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------
u0_temp_sensor_clk_temp 0 0 0 1000000 0 0 50000 N
u0_temp_sensor_clk_apb0 0 0 0
49500000 0 0 50000 N
$ cat /sys/class/hwmon/hwmon0/temp1_enable
0
$ cat /sys/class/hwmon/hwmon0/temp1_input
cat: read error: No data available
[runtime_pm on]
When runtime_pm is turned on, sfctemp will automatically enter
the suspend state and close clk after the system is started.
$ cat /sys/kernel/debug/clk/clk_summary | grep "temp_sensor"
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------
u0_temp_sensor_clk_temp 0 0 0 1000000 0 0 50000 N
u0_temp_sensor_clk_apb0 0 0 0
49500000 0 0 50000 N
when 'cat /sys/class/hwmon/hwmon0/temp1_input', it will call
starfive_temp_resume, enable clk and put sfctemp into power on state.
$ cat /sys/class/hwmon/hwmon0/temp1_input
46235
After the interrupt is generated and the sensor value is obtained, it
will enter the suspend state again. so, hardware-enable-stats is always 'N'.
Of course, in this mode (runtime_pm on), it also supports the opening
and closing of functions (in fact, clk is not directly operated, and the
opening and closing of clk are controlled by runtime_pm)
$ cat /sys/class/hwmon/hwmon0/temp1_input
46235
$ cat /sys/class/hwmon/hwmon0/temp1_enable
1
$ echo 0 > /sys/class/hwmon/hwmon0/temp1_enable
$ cat /sys/class/hwmon/hwmon0/temp1_enable
0
$ cat /sys/class/hwmon/hwmon0/temp1_input
cat: read error: No data available
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
andy.hu [Tue, 17 Jan 2023 11:04:59 +0000 (11:04 +0000)]
Merge branch 'CR_2956_gpu_shanlong.li' into 'jh7110-5.15.y-devel'
CR_2956: gpu:driver: fix up hibernation resume problem
See merge request sdk/linux!672
andy.hu [Tue, 17 Jan 2023 10:18:44 +0000 (10:18 +0000)]
Merge branch 'CR_3027_pinctrl_hal.feng' into 'jh7110-5.15.y-devel'
CR 3027 pinctrl hal.feng
See merge request sdk/linux!671
andy.hu [Tue, 17 Jan 2023 10:15:11 +0000 (10:15 +0000)]
Merge branch 'CR_3058_hibernation_clocktree_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_3058_hibernation_clocktree_Xingyu.Wu
See merge request sdk/linux!670
Changhuang Liang [Tue, 17 Jan 2023 06:17:28 +0000 (14:17 +0800)]
media: starfive: Modify support imx219 compile to module
Modify support imx219 compile to module.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
shanlong.li [Mon, 16 Jan 2023 08:43:09 +0000 (00:43 -0800)]
gpu:driver: fix up hibernation resume problem
fix up hibernation resume problem
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
Hal Feng [Fri, 13 Jan 2023 08:35:54 +0000 (16:35 +0800)]
pinctrl: starfive: Save all register values when suspending and restore them when resuming
Restore the other registers besides irq registers when resuming.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Xingyu Wu [Fri, 13 Jan 2023 03:09:03 +0000 (11:09 +0800)]
clk: starfive: Fixed UART3-5 error after resume
Fixed UART3-5 error after hibernation by adjusting register shift.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
andy.hu [Wed, 11 Jan 2023 12:02:08 +0000 (12:02 +0000)]
Merge branch 'CR_3027_pinctrl_hal.feng' into 'jh7110-5.15.y-devel'
CR 3027 pinctrl hal.feng
See merge request sdk/linux!669
andy.hu [Wed, 11 Jan 2023 11:56:06 +0000 (11:56 +0000)]
Merge branch 'CR_3122_fix_usb_resume_device_minda' into 'jh7110-5.15.y-devel'
CR_3122 usb: phy: init phy in resume function
See merge request sdk/linux!667
andy.hu [Wed, 11 Jan 2023 11:06:58 +0000 (11:06 +0000)]
Merge branch 'CR_3051_ts_515_changhuang.liang' into 'jh7110-5.15.y-devel'
CR_3051_ts_515_changhuang.liang input: touchscreen: tinker_ft5406: Delete unused code.
See merge request sdk/linux!661
andy.hu [Wed, 11 Jan 2023 11:06:13 +0000 (11:06 +0000)]
Merge branch 'CR_3054_vin_system_pm_changhuang.liang' into 'jh7110-5.15.y-devel'
CR_3054_vin_system_pm_changhuang.liang media: starfive: Delete unused USE_MEDIA_PIPELINE macro code
See merge request sdk/linux!665
andy.hu [Wed, 11 Jan 2023 11:04:45 +0000 (11:04 +0000)]
Merge branch 'CR_3025_hibernation_tdm_walker.chen' into 'jh7110-5.15.y-devel'
CR_3025_hibernation_tdm_walker.chen
See merge request sdk/linux!666
andy.hu [Wed, 11 Jan 2023 11:03:59 +0000 (11:03 +0000)]
Merge branch 'CR_3058_hibernation_clocktree_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_3058_hibernation_clocktree_Xingyu.Wu
See merge request sdk/linux!668
andy.hu [Wed, 11 Jan 2023 11:02:42 +0000 (11:02 +0000)]
Merge branch 'CR_2964_hibernation_spdif_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_2964_hibernation_spdif_Xingyu.Wu
See merge request sdk/linux!664
andy.hu [Wed, 11 Jan 2023 11:01:53 +0000 (11:01 +0000)]
Merge branch 'CR_3021_hibernation_pwmdac_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_3021_hibernation_pwmdac_Xingyu.Wu
See merge request sdk/linux!663
Xingyu Wu [Fri, 6 Jan 2023 07:12:23 +0000 (15:12 +0800)]
clk: starfive: Add funtions of saving and restoring data about SYS, AON and STG
Add 'save_context' ops to save register value of clock and
'restore_context' ops to restore the value to register.
The ops only suitable for SYS, AON and STG clock tree not ISP and VOUT.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
minda.chen [Wed, 11 Jan 2023 08:58:11 +0000 (16:58 +0800)]
usb: phy: init phy in resume function
usb phy will be reset in suspend procedure. After resume.
Some devices can not work. In usb resume, init phy again.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
Walker Chen [Wed, 11 Jan 2023 09:31:14 +0000 (17:31 +0800)]
CR_3025_Hibernation_TDM_Walker.chen
Fixed playback failed after hibernation by saving and restoring registers' data.
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Changhuang Liang [Wed, 11 Jan 2023 07:53:26 +0000 (15:53 +0800)]
media: starfive: Update VIN system PM operation
Update VIN system PM operation, fixed multi open the same video node
cause resume fail.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Wed, 11 Jan 2023 07:32:03 +0000 (15:32 +0800)]
media: starfive: stf_video: Multi open only set power one time
Multi open the same video node only set power one time.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Wed, 11 Jan 2023 07:22:38 +0000 (15:22 +0800)]
media: starfive: Delete unused USE_MEDIA_PIPELINE macro code
Delete unused USE_MEDIA_PIPELINE macro code.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Xingyu Wu [Wed, 11 Jan 2023 03:08:28 +0000 (11:08 +0800)]
sound: starfive: pwmdac: Fixed playback failed after hibernation
Fixed playback failed after hibernation by saving and restoring
register data.
Fixed error when open PWMDAC_PCM.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Wed, 11 Jan 2023 02:22:29 +0000 (10:22 +0800)]
sound: starfive: spdif: Fixed playback failed after hibernation
Fixed playback failed after hibernation by saving and restoring registers' data.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Hal Feng [Fri, 6 Jan 2023 10:12:33 +0000 (18:12 +0800)]
pinctrl: starfive: Save register values when suspending and restore them when resuming
Restore the register configuration after resuming.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Changhuang Liang [Mon, 9 Jan 2023 03:31:36 +0000 (11:31 +0800)]
input: touchscreen: tinker_ft5406: Update log show
Update log show.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Mon, 9 Jan 2023 03:13:11 +0000 (11:13 +0800)]
input: touchscreen: tinker_ft5406: Enable multipoint function
Enable multipoint function.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Mon, 9 Jan 2023 02:39:29 +0000 (10:39 +0800)]
input: touchscreen: tinker_ft5406: Delete unused code.
Delete unused code avoid warning.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Hal Feng [Fri, 6 Jan 2023 08:15:21 +0000 (16:15 +0800)]
pinctrl: starfive: Move pm ops to pinctrl-starfive-jh7110.c
Because different SoCs have their own registers. We want to
save all registers in the pm suspend function and restore
them in the pm resume function.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
andy.hu [Fri, 6 Jan 2023 07:26:35 +0000 (07:26 +0000)]
Merge branch 'CR_3049_Hibernation_mason.huo' into 'jh7110-5.15.y-devel'
CR_3049 Add hibernation feature
See merge request sdk/linux!658
William Qiu [Fri, 6 Jan 2023 04:26:45 +0000 (12:26 +0800)]
riscv: starfive: sdio: modify and add sd card config
modify and add sd card config, sush as 'max-frequency'
'pinctrl-names'.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
andy.hu [Fri, 6 Jan 2023 06:08:13 +0000 (06:08 +0000)]
Merge branch 'CR_2828_perf_support_minda' into 'jh7110-5.15.y-devel'
CR_2828 add perf_patch
See merge request sdk/linux!641
William Qiu [Fri, 6 Jan 2023 01:55:45 +0000 (09:55 +0800)]
Hibernation: canfd: Add system PM API for can/canfd
Add system PM API for can/canfd.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
mason.huo [Tue, 3 Jan 2023 05:39:30 +0000 (13:39 +0800)]
irqchip/irq-sifive-plic: Add syscore callbacks for hibernation
The priority and enable registers of plic will be reset
during hibernation power cycle in poweroff mode,
add the syscore callbacks to save/restore those registers.
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
Sia Jee Heng [Tue, 3 Jan 2023 02:21:15 +0000 (10:21 +0800)]
RISCV: Support pmd_leaf() in the function kernel_page_present()
Update kernel_page_present() function to support pmd_leaf().
Function kernel_page_present() will be invoked when hibernation is
started.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
ziv.xu [Thu, 27 Oct 2022 02:52:50 +0000 (10:52 +0800)]
timer-starfive:add pm ops for timer
add system pm ops for timer
Signed-off-by: ziv.xu <ziv.xu@starfive.com>
mason.huo [Thu, 13 Oct 2022 01:25:12 +0000 (09:25 +0800)]
rsicv: deconfig: Add hibernation and swap partition
Enable the hibernation feature, and config the default
hibernation swap partition by partition label.
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
Sia Jee Heng [Sun, 6 Nov 2022 11:24:44 +0000 (19:24 +0800)]
riscv: kernel: Support hibernation resume for JH7110
Further expand the support for hibernation resume so that the hibernated
image can be restore from the disk.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Sia Jee Heng [Mon, 17 Oct 2022 02:25:05 +0000 (10:25 +0800)]
riscv: kernel: Expand functionlity of swsusp_arch_suspend for JH7110
Futher expand the functionality of the swsusp_arch_suspend so that the
hibernated image can be written to the disk and resume from the
hibernated image.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
Sia Jee Heng [Thu, 1 Sep 2022 07:47:11 +0000 (15:47 +0800)]
riscv: kernel: Add support for hibernate/suspend to disk
The implementation assumes that exactly the same kernel is booted on the
same hardware.
We save the build number and date to the swap header so that we guarantee
not to resume with a different kernel upon booted up the hibernated image.
swsusp_arch_resume() and swsusp_arch_suspend() are coded as dummy
functions for now and shall complete in the subsequent patches.
Signed-off-by: Sia Jee Heng <jeeheng.sia@starfivetech.com>
mason.huo [Wed, 21 Sep 2022 10:40:44 +0000 (18:40 +0800)]
riscv: deconfig: Enable system suspend and pm test
Config the system suspend feature, enable pm test feature.
Signed-off-by: mason.huo <mason.huo@starfivetech.com>
minda.chen [Wed, 7 Dec 2022 09:49:23 +0000 (17:49 +0800)]
dts: configs: add perf events config
add 7110 perf support
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
João Mário Domingos [Tue, 16 Nov 2021 15:48:12 +0000 (15:48 +0000)]
RISC-V: Added HiFive Unmatched PMU events
This patch contains all the available events for the HiFive Unmatched performance monitoring unit.
Depends on patch [3], for the base mapfile.csv file.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
João Mário Domingos [Tue, 16 Nov 2021 15:48:11 +0000 (15:48 +0000)]
RISC-V: Added generic pmu-events mapfile
The pmu-events now supports custom events for RISC-V, plus the cycle,
time and instret events were defined.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
João Mário Domingos [Tue, 16 Nov 2021 15:48:10 +0000 (15:48 +0000)]
RISC-V: Support CPUID for risc-v in perf
This patch creates the header.c file for the risc-v architecture and introduces support for
PMU identification through sysfs.
It is now possible to configure pmu-events in risc-v.
Depends on patch [1], that introduces the id sysfs file.
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
João Mário Domingos [Tue, 16 Nov 2021 15:48:09 +0000 (15:48 +0000)]
RISC-V: Create unique identification for SoC PMU
The SBI PMU platform driver did not provide any identification for
perf events matching. This patch introduces a new sysfs file inside the
platform device (soc:pmu/id) for pmu identification.
The identification is a 64-bit value generated as:
[63-32]: mvendorid;
[31]: marchid[MSB];
[30-16]: marchid[15-0];
[15-0]: mimpid[15MSBs];
The CSRs are detailed in the RISC-V privileged spec [1].
The marchid is split in MSB + 15LSBs, due to the MSB being used for
open-source architecture identification.
[1] https://github.com/riscv/riscv-isa-manual
Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
Atish Patra [Wed, 8 Sep 2021 20:01:07 +0000 (13:01 -0700)]
MAINTAINERS: Add entry for RISC-V PMU drivers
Add myself and Anup as maintainer for RISC-V PMU drivers.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 26 May 2021 00:51:35 +0000 (17:51 -0700)]
Documentation: riscv: Remove the old documentation
The existing pmu documentation describes the limitation of perf
infrastructure in RISC-V ISA and limited feature set of perf in RISC-V.
However, SBI PMU extension and sscofpmf extension(ISA extension) allows to
implement most of the required features of perf. Remove the old
documentation which is not accurate anymore.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Fri, 27 Aug 2021 22:03:43 +0000 (15:03 -0700)]
RISC-V: Add sscofpmf extension support
The sscofpmf extension allows counter overflow and filtering for
programmable counters. Enable the perf driver to handle the overflow
interrupt. The overflow interrupt is a hart local interrupt.
Thus, per cpu overflow interrupts are setup as a child under the root
INTC irq domain.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Thu, 24 Mar 2022 08:20:57 +0000 (16:20 +0800)]
RISC-V: Improve /proc/cpuinfo output for ISA extensions
Currently, the /proc/cpuinfo outputs the entire riscv,isa string which
is not ideal when we have multiple ISA extensions present in the ISA
string. Some of them may not be enabled in kernel as well.
Parse only the enabled ISA extension and print them in a separate row.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 9 Feb 2022 07:46:07 +0000 (23:46 -0800)]
RISC-V: Do no continue isa string parsing without correct XLEN
The isa string should begin with either rv64 or rv32. Otherwise, it is
an incorrect isa string. Currently, the string parsing continues even if
it doesnot begin with current XLEN.
Fix this by checking if it found "rv64" or "rv32" in the beginning.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Tue, 8 Feb 2022 22:58:38 +0000 (14:58 -0800)]
RISC-V: Implement multi-letter ISA extension probing framework
Multi-letter extensions can be probed using exising
riscv_isa_extension_available API now. It doesn't support versioning
right now as there is no use case for it.
Individual extension specific implementation will be added during
each extension support.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Tsukasa OI [Sat, 12 Feb 2022 06:30:01 +0000 (15:30 +0900)]
RISC-V: Extract multi-letter extension names from "riscv, isa"
Currently, there is no usage for version numbers in extensions as
any ratified non base ISA extension will always at v1.0.
Extract the extension names in place for future parsing.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
[Improved commit text and comments]
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Tsukasa OI [Sat, 12 Feb 2022 06:30:00 +0000 (15:30 +0900)]
RISC-V: Minimal parser for "riscv, isa" strings
Current hart ISA ("riscv,isa") parser don't correctly parse:
1. Multi-letter extensions
2. Version numbers
All ISA extensions ratified recently has multi-letter extensions
(except 'H'). The current "riscv,isa" parser that is easily confused
by multi-letter extensions and "p" in version numbers can be a huge
problem for adding new extensions through the device tree.
Leaving it would create incompatible hacks and would make "riscv,isa"
value unreliable.
This commit implements minimal parser for "riscv,isa" strings. With this,
we can safely ignore multi-letter extensions and version numbers.
[Improved commit text and fixed a bug around 's' in base extension]
Signed-off-by: Atish Patra <atishp@rivosinc.com>
[Fixed workaround for QEMU]
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tsukasa OI [Sat, 12 Feb 2022 06:29:59 +0000 (15:29 +0900)]
RISC-V: Correctly print supported extensions
This commit replaces BITS_PER_LONG with number of alphabet letters.
Current ISA pretty-printing code expects extension 'a' (bit 0) through
'z' (bit 25). Although bit 26 and higher is not currently used (thus never
cause an issue in practice), it will be an annoying problem if we start to
use those in the future.
This commit disables printing high bits for now.
Reviewed-by: Anup Patel <anup@brainfault.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 17 Mar 2021 23:54:14 +0000 (16:54 -0700)]
RISC-V: Add perf platform driver based on SBI PMU extension
RISC-V SBI specification added a PMU extension that allows to configure
start/stop any pmu counter. The RISC-V perf can use most of the generic
perf features except interrupt overflow and event filtering based on
privilege mode which will be added in future.
It also allows to monitor a handful of firmware counters that can provide
insights into firmware activity during a performance analysis.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Thu, 24 Mar 2022 09:04:38 +0000 (17:04 +0800)]
RISC-V: Add RISC-V SBI PMU extension definitions
This patch adds all the definitions defined by the SBI PMU extension.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 17 Mar 2021 23:31:46 +0000 (16:31 -0700)]
RISC-V: Add a simple platform driver for RISC-V legacy perf
The old RISC-V perf implementation allowed counting of only
cycle/instruction counters using perf. Restore that feature by implementing
a simple platform driver under a separate config to provide backward
compatibility. Any existing software stack will continue to work as it is.
However, it provides an easy way out in future where we can remove the
legacy driver.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 17 Mar 2021 23:18:17 +0000 (16:18 -0700)]
RISC-V: Add a perf core library for pmu drivers
Implement a perf core library that can support all the essential perf
features in future. It can also accommodate any type of PMU implementation
in future. Currently, both SBI based perf driver and legacy driver
implemented uses the library. Most of the common perf functionalities
are kept in this core library wile PMU specific driver can implement PMU
specific features. For example, the SBI specific functionality will be
implemented in the SBI specific driver.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 17 Mar 2021 22:52:47 +0000 (15:52 -0700)]
RISC-V: Add CSR encodings for all HPMCOUNTERS
Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are
accessible in S-mode.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Atish Patra [Wed, 17 Mar 2021 22:36:30 +0000 (15:36 -0700)]
RISC-V: Remove the current perf implementation
The current perf implementation in RISC-V is not very useful as it can not
count any events other than cycle/instructions. Moreover, perf record
can not be used or the events can not be started or stopped.
Remove the implementation now for a better platform driver in future
that will implement most of the missing functionality.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
andy.hu [Thu, 29 Dec 2022 04:29:17 +0000 (04:29 +0000)]
Merge branch 'CR_2861_ts_515_changhuang.liang' into 'jh7110-5.15.y-devel'
CR_2861_ts_515_changhuang.liang input: touchscreen: Add tinker_ft5406 driver support
See merge request sdk/linux!654
andy.hu [Thu, 29 Dec 2022 03:12:40 +0000 (03:12 +0000)]
Merge branch 'CR_2933_MMC_515_william.qiu' into 'jh7110-5.15.y-devel'
CR_2933_515 riscv: dts: mmc: delete mmc1 config
See merge request sdk/linux!651
andy.hu [Thu, 29 Dec 2022 03:11:05 +0000 (03:11 +0000)]
Merge branch 'CR_2951_515_ac101_compile_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_2951_515_ac101_compile_Xingyu.Wu
See merge request sdk/linux!655
Changhuang Liang [Thu, 22 Dec 2022 08:07:23 +0000 (16:07 +0800)]
input: touchscreen: tinker_ft5406: Fixed show more error log bug
Fixed show more error log bug when not attach the touchscreen.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Thu, 22 Dec 2022 02:59:23 +0000 (10:59 +0800)]
riscv: defconfig: Enable touchscreen
Enable touchscreen TINKER FT5406
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Xingyu Wu [Thu, 22 Dec 2022 07:00:48 +0000 (15:00 +0800)]
sound: codecs: ac101: Fixed warning when compiling
Removed the useless part and fixed warning.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Changhuang Liang [Thu, 22 Dec 2022 02:57:08 +0000 (10:57 +0800)]
riscv: dts: starfive: Add tinker_ft5406 touchscreen node
Add tinker_ft5406 touchscreen node.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Thu, 22 Dec 2022 02:31:15 +0000 (10:31 +0800)]
input: touchscreen: tinker_ft5406: Add open&close ioctl
Add open&close ioctl.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Changhuang Liang [Wed, 21 Dec 2022 08:20:04 +0000 (16:20 +0800)]
input: touchscreen: Add tinker_ft5406 driver support
Add tinker_ft5406 driver support
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
William Qiu [Tue, 20 Dec 2022 10:56:59 +0000 (18:56 +0800)]
riscv: dts: mmc: delete mmc1 config
delete mmc1 config, default use mmc0
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
andy.hu [Mon, 19 Dec 2022 04:02:54 +0000 (04:02 +0000)]
Merge branch 'CR_2868_515_evb_rgb2hdmi_shengyang.chen' into 'jh7110-5.15.y-devel'
CR_2868: riscv: linux: vout: fix rgb2hdmi display problem
See merge request sdk/linux!639
andy.hu [Mon, 19 Dec 2022 04:00:26 +0000 (04:00 +0000)]
Merge branch 'CR_2069_515_evb_cusor_keith.zhao' into 'jh7110-5.15.y-devel'
CR_2069: riscv: linux: vout: fix cusor problem
See merge request sdk/linux!647
andy.hu [Mon, 19 Dec 2022 03:55:01 +0000 (03:55 +0000)]
Merge branch 'CR_2888_515_clocktree_pll0_Xingyu.Wu' into 'jh7110-5.15.y-devel'
CR_2888_515_clocktree_pll0_Xingyu.Wu
See merge request sdk/linux!644
andy.hu [Mon, 19 Dec 2022 03:52:06 +0000 (03:52 +0000)]
Merge branch 'CR_2871_MMC_515_william.qiu' into 'jh7110-5.15.y-devel'
CR_2871riscv: dts: mmc:modify mmc1 config
See merge request sdk/linux!643
andy.hu [Mon, 19 Dec 2022 03:49:44 +0000 (03:49 +0000)]
Merge branch 'CR_2865_RNG_jiajie.ho' into 'jh7110-5.15.y-devel'
CR_2865: hwrng: Reworked driver for speed performance and efficiency
See merge request sdk/linux!640
shengyang.chen [Fri, 16 Dec 2022 08:15:39 +0000 (16:15 +0800)]
riscv: linux: vout: fix cusor problem
fix cusor bluring problem of debian
Signed-off-by: keith <keith.zhao@starfivetech.com>
William Qiu [Thu, 15 Dec 2022 09:03:28 +0000 (17:03 +0800)]
riscv: dts: mmc:modify mmc1 config
modify mmc1 config
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Xingyu Wu [Thu, 15 Dec 2022 06:48:40 +0000 (14:48 +0800)]
clk: starfive: pll: Remove high frequency of PLL0
Remove high frequency of PLL0 and make sure PLL0 max frequency is 1.5GHz.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Xingyu Wu [Thu, 15 Dec 2022 06:17:59 +0000 (14:17 +0800)]
clk: starfive: Change divider value of cpu_core clock
Change divider value to make sure the frequency is half of PLL0.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>