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RISC-V: Add CSR encodings for all HPMCOUNTERS
authorAtish Patra <atish.patra@wdc.com>
Wed, 17 Mar 2021 22:52:47 +0000 (15:52 -0700)
committerminda.chen <minda.chen@starfivetech.com>
Tue, 3 Jan 2023 06:26:17 +0000 (14:26 +0800)
commit80b4eaf7a803baaf025f75f6b4e7cda2115435b1
tree4e786100730f4e510cd673a82bea1d156c8486fatree | snapshot
parentd3e58d74917cc81279dd8ba0c1ce8640443e12ddcommit | diff
RISC-V: Add CSR encodings for all HPMCOUNTERS

Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are
accessible in S-mode.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
arch/riscv/include/asm/csr.h diff | blob | history
Domain: System / Kernel;