Zhao halley [Thu, 31 May 2012 09:00:24 +0000 (17:00 +0800)]
add pa_load_save_pl3 for YUY2-->YV12 conversion (SNB/ILK)
Gwenole Beauchesne [Mon, 28 May 2012 14:07:49 +0000 (04:07 -1000)]
jpeg: fix submission of quantization and Huffman tables.
Upload quantiser and Huffman tables only if they are marked as dirty.
i.e. the user requested to load them.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Dmitry Ermilov [Fri, 15 Jun 2012 04:24:37 +0000 (00:24 -0400)]
Implementation for i965_SyncSurface and i965_QuerySurfaceStatus
(cherry picked from commit
25673c458932caa09ae3f47c6dbe7e040dbae032)
Xiang, Haihao [Mon, 11 Jun 2012 02:46:22 +0000 (10:46 +0800)]
silence compiler warning
gen6_mfc.c: In function ‘gen6_mfc_brc_init’:
gen6_mfc.c:814:44: warning: initialization from incompatible pointer type [enabled by default]
gen6_mfc.c: In function ‘gen6_mfc_avc_prepare’:
gen6_mfc.c:1058:18: warning: unused variable ‘rate_control_mode’ [-Wunused-variable]
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 11 Jun 2012 01:52:47 +0000 (09:52 +0800)]
Fix slice delta for CBR mode
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Rogozhkin, Dmitry V [Mon, 11 Jun 2012 01:45:41 +0000 (09:45 +0800)]
New BRC algorithm to match HRD
It reduces the number of recoding as well.
Signed-off-by: Rogozhkin, Dmitry V <dmitry.v.rogozhkin@intel.com>
Xiang, Haihao [Thu, 7 Jun 2012 06:48:25 +0000 (14:48 +0800)]
Currently only SNB supports packed YUV image
Check the returned status as well.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Jun 2012 05:53:42 +0000 (13:53 +0800)]
Fix coded buffer size calculating for CBR mode
The encoded frame includes not only all macroblocks,
but also PPS/SPS/Slice headers.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Jun 2012 01:02:30 +0000 (09:02 +0800)]
Fix QP setting for CBR mode
The QP specified in MFX_AVC_SLICE_STATE is also used as the starting
QP in the first MB of a slice. In addition, add assertions for QP releated
setting for 8-bit pixel bit-depth support
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Rogozhkin, Dmitry V <dmitry.v.rogozhkin@intel.com>
Xiang, Haihao [Thu, 31 May 2012 10:49:44 +0000 (18:49 +0800)]
Accept packed misc data package such as SEI data
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Tested-by: Dmitry Ermilov <dmitry.ermilov@intel.com>
Xiang, Haihao [Wed, 30 May 2012 05:12:58 +0000 (13:12 +0800)]
Fix weight denom for implicit weight tables on SNB for encoding
It is the same of commit fd9c532
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 30 May 2012 01:21:38 +0000 (09:21 +0800)]
Don't render the target surface with background if alpha value is 0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 30 May 2012 01:18:59 +0000 (09:18 +0800)]
clear background under right context
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Rogozhkin, Dmitry V [Tue, 29 May 2012 00:05:20 +0000 (08:05 +0800)]
Optimal parameters for Intra prediction mode
Xiang, Haihao [Thu, 24 May 2012 01:14:45 +0000 (09:14 +0800)]
Fix the regression caused by
d90a5ea9f21bc20f35c26457dec57f41f7a184d1
The DNDI kernel is still inapplicable.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao halley [Thu, 17 May 2012 07:49:34 +0000 (15:49 +0800)]
add yuyv->nv12 conversion in image processing
Zhao halley [Wed, 16 May 2012 23:58:31 +0000 (07:58 +0800)]
add YUYV to NV12 conversion(pa_load_save_nv12.asm etc)
Zhao halley [Thu, 17 May 2012 07:39:43 +0000 (15:39 +0800)]
add YV12 to YUY2 conversion
Zhao halley [Thu, 3 May 2012 02:50:51 +0000 (10:50 +0800)]
add pl3_load_save_pa.asm etc
Zhao halley [Thu, 17 May 2012 07:28:16 +0000 (15:28 +0800)]
add NV12 to YUY2 color conversion
Halley Zhao [Fri, 27 Apr 2012 05:54:13 +0000 (13:54 +0800)]
add nv12_load_save_pa.asm
Zhao halley [Thu, 17 May 2012 07:19:11 +0000 (15:19 +0800)]
add 422/YUY2 to surface formats
Zhou Chang [Mon, 14 May 2012 07:35:53 +0000 (15:35 +0800)]
Enable Stream-Out on IVB
Signed-off-by: Zhou Chang <chang.zhou@intel.com>
Haitao Huang [Fri, 11 May 2012 13:34:47 +0000 (08:34 -0500)]
src/Android.mk: add new files for mfc, gpe, enc
Change-Id: I76a344b6d44ebc00eef507e5c633c0722c3b201a
Signed-off-by: Haitao Huang <haitao.huang@intel.com>
Haitao Huang [Fri, 11 May 2012 13:34:45 +0000 (08:34 -0500)]
intel-driver: initial porting to Android ICS
Added Android make files, conditionally compile PutSurface
implementation, which is not needed for Android ICS.
For: AIA-418
Change-Id: Ifd6a6ec2dabd8ee1ad4d34a41b3d274f8817f965
Depends-Change-Id: I2feabf6941379ef4d756e942f30eba059de641f1
Depends-Change-Id: I3452f6e784f11c39d4d925c57cd844bd4cc9dc9e
Signed-off-by: Haitao Huang <haitao.huang@intel.com>
Gwenole Beauchesne [Fri, 11 May 2012 15:18:36 +0000 (17:18 +0200)]
jpeg: drop explicit check for VA/JPEG decoding API.
Staging branch VA driver needs to be built against a staging branch
libva. So, the VA/JPEG decoding API is present and actually mandatory
for VA-API >= 0.34.
Gwenole Beauchesne [Fri, 11 May 2012 14:26:22 +0000 (16:26 +0200)]
jpeg: fix configure check for newer API.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Haitao Huang [Fri, 11 May 2012 13:34:46 +0000 (08:34 -0500)]
jpeg: update to latest API.
Signed-off-by: Haitao Huang <haitao.huang@intel.com>
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Fri, 11 May 2012 15:17:37 +0000 (17:17 +0200)]
configure: enforce build against VA-API 0.34.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Tue, 8 May 2012 07:37:37 +0000 (15:37 +0800)]
ENC: Enable all Intra mode on Ivybridge
The same fields will be ignored on Sandybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 4 May 2012 08:34:55 +0000 (16:34 +0800)]
VPP: it should be float for normalized_x/y
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 4 May 2012 08:33:47 +0000 (16:33 +0800)]
VPP: pass the origin of source region to vpp kernel
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 4 May 2012 03:05:52 +0000 (11:05 +0800)]
Fix the error code for unsupported resolution
Thank Gwenole for pointing it out
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
d0dfefde77ebe6093e304a84df796c6e1157f00a)
Xiang, Haihao [Fri, 4 May 2012 02:58:48 +0000 (10:58 +0800)]
VPP: Render target surface with background color
Currently ignore alpha value. We will fix it once the
alpha blend kernel is ready
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 3 May 2012 05:45:50 +0000 (13:45 +0800)]
MPEG-2: Fix MFX_QM_STATE command on Ivybridge
If load_intra_quantiser_matrix/load_non_intra_quantiser_matrix is set to 0, then
there is no change to quantisation matrix. In this case, submit MFX_QM_STATE
with previous setting
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
1c00e5916b59439fc7d8b0a59e82bc6bce2eb2de)
Conflicts:
src/gen7_mfd.c
Xiang, Haihao [Wed, 2 May 2012 08:23:59 +0000 (16:23 +0800)]
Enlarge some internal buffer for H.264 decoding on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c3f06e2b32197d403d96b548b6b7589b245e8aaa)
Xiang, Haihao [Wed, 25 Apr 2012 05:14:43 +0000 (13:14 +0800)]
Support mixed mode for VME
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 23 Apr 2012 08:35:36 +0000 (16:35 +0800)]
Fix the filling of MFC batchbuffer for software path
VME has output more macroblock messages which should be used
when filling the MFC batchbuffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhou Chang [Fri, 20 Apr 2012 08:20:00 +0000 (16:20 +0800)]
Added workaroud for CBR support in IVB.
Xiang, Haihao [Thu, 19 Apr 2012 06:45:03 +0000 (14:45 +0800)]
Remove hard-coded code.
Istead, the MFX setting depends on the user setting parameters
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 19 Apr 2012 05:11:44 +0000 (13:11 +0800)]
Don't use DNDI kernel on Ivybridge temporarily
We will integrate the right kernel for DN/DI on Ivybridge as soon as possible.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 19 Apr 2012 03:24:06 +0000 (11:24 +0800)]
Don't call VPP if the kernel isn't ready.
This avoids segment fault in VPP
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 19 Apr 2012 02:22:34 +0000 (10:22 +0800)]
Fix parameter setting for AVS on Ivybridge
DU multiplied by width in SURFACE_STATE must be less
than 16 for the sample_8x8 message.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 13 Apr 2012 02:44:57 +0000 (10:44 +0800)]
Add support for new Ivybridge chipset
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
4e3a3146128c6f790c9f586c2141ae96955069cd)
Xiang, Haihao [Tue, 10 Apr 2012 07:27:08 +0000 (15:27 +0800)]
Don't need to expand MVs on Ivybridge
The MVs in the VME output are consistent to MFC on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 10 Apr 2012 07:05:56 +0000 (15:05 +0800)]
Fix MvSize on Ivybridge
The MvSize in the writeback message on Sandybridge is inconsistent to
MFC, however it is consistent to MFC on Ivybridge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 10 Apr 2012 01:34:35 +0000 (09:34 +0800)]
Correct the setting for search path in VME_STATE
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 10 Apr 2012 01:39:47 +0000 (09:39 +0800)]
Fix the length of writeback message for Inter frame
A GRF register consists of two OWords
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhou Chang [Fri, 6 Apr 2012 07:57:40 +0000 (15:57 +0800)]
Change to none-block in CBR mode
Zhou Chang [Fri, 6 Apr 2012 07:57:13 +0000 (15:57 +0800)]
Fixed multipul slices edge prediction issue for Intra
Zhou Chang [Fri, 6 Apr 2012 07:56:42 +0000 (15:56 +0800)]
Added interlace mode check, just a workaround.
Xiang, Haihao [Fri, 6 Apr 2012 07:46:18 +0000 (15:46 +0800)]
Support sub-partition for Inter frame
Also support 32 MVs
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 6 Apr 2012 07:34:20 +0000 (15:34 +0800)]
Directly use the size of the output MV from VME to format MFC_AVC_PAK_OBJECT command
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 6 Apr 2012 03:25:00 +0000 (11:25 +0800)]
Update LUT_MV table
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 6 Apr 2012 03:23:01 +0000 (11:23 +0800)]
Expand 8 MVs
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 6 Apr 2012 00:45:32 +0000 (08:45 +0800)]
Correct the register region in VME kernel
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 5 Apr 2012 08:40:13 +0000 (16:40 +0800)]
Support sub-macroblocks for Inter frame
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 5 Apr 2012 08:38:51 +0000 (16:38 +0800)]
Use the output from VME to format MFC_AVC_PAK_OBJEC command for Inter frame
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 5 Apr 2012 07:51:25 +0000 (15:51 +0800)]
Output more information in VME output buffer for Inter frame
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 5 Apr 2012 07:49:42 +0000 (15:49 +0800)]
Expand the VME output buffer for Inter frame
Prepare for 32 MVs(128 bytes) and other information(32 bytes) from VME. In addition, use
macros instead of magic numbers
Signed-off-by :Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Mon, 12 Mar 2012 14:30:13 +0000 (15:30 +0100)]
render: fix rendering of interlaced surfaces.
Handle bob-deinterlacing flags passed to vaPutSurface().
i.e. VA_TOP_FIELD|VA_BOTTOM_FIELD.
Avoid advanced deinterlacing kernels as they allocate extra temporary
surfaces, which are useless for such simple tasks. i.e. display either
field of an interlaced surface.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Wed, 4 Apr 2012 08:52:27 +0000 (10:52 +0200)]
vpp: drop "flags" field in pipeline caps.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Xiang, Haihao [Sun, 1 Apr 2012 02:21:19 +0000 (10:21 +0800)]
Update LUT_MbMode for set 0
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Sun, 1 Apr 2012 02:18:10 +0000 (10:18 +0800)]
Only disable INTRA_8x8 if transform_8x8_mode_flag isn't set
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Gwenole Beauchesne [Thu, 29 Mar 2012 12:13:47 +0000 (14:13 +0200)]
mpeg2: propagate reference surfaces to other slots.
Fill in remaining reference surfaces as recommanded in HW specs.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Gwenole Beauchesne [Thu, 15 Mar 2012 13:41:47 +0000 (14:41 +0100)]
mpeg2: fix construction of reference frames list (SNB, IVB).
Fix construction of reference frames list for interlaced streams.
In this case, the array is indexed by frame store ID >> 1 where
bit 0 of frame store ID represents top (0) or bottom (1) field.
Besides, current render target can also be used as a reference
while decoding the second field.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
14f70559b516030d141cce09db54cf49d11df9b2)
Gwenole Beauchesne [Thu, 15 Mar 2012 13:41:47 +0000 (14:41 +0100)]
mpeg2: fix reference surfaces construction (IVB).
Avoid an assert() since we were assigning a reference surface even
if it did not have any backing store.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
18212d42c5dfee047094ae67914c2b2b630ad99e)
Gwenole Beauchesne [Mon, 27 Feb 2012 12:57:09 +0000 (13:57 +0100)]
mpeg2: fix TFF calculation (SNB).
Gen6 has specific requirements for the TFF flag, and thus has different
semantics than Gen7 (IVB). In particular, HW uses picture_structure and
TFF flag to determine the correct field to render.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
01c37fad8c991714026d6a995e9e35cc7865933e)
Gwenole Beauchesne [Mon, 12 Mar 2012 15:40:59 +0000 (16:40 +0100)]
mpeg2: fix incorrect slice_vertical_position from codec layers.
Correctly emit slice_vertical_position, as per the definition from
the bitstream, to the HW decoder (MFD_MPEG2_BSD_OBJECT).
Add workaround for players that have not fixed their usage of
slice_vertical_position. That field shall represent the slice vertical
position as it comes from the bitstream.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
298dc939835e3080c9330b4e52e8dfac25bf3060)
Conflicts:
NEWS
Gwenole Beauchesne [Sun, 18 Mar 2012 07:59:46 +0000 (08:59 +0100)]
Add WARN_ONCE() helper macro.
Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
(cherry picked from commit
2447c981a84cd9dc1eddf8e4258cef555503024f)
Zhou Chang [Wed, 28 Mar 2012 06:37:50 +0000 (14:37 +0800)]
Fixed CBR mode missed issue in SNB.
Xiang, Haihao [Mon, 26 Mar 2012 07:11:15 +0000 (15:11 +0800)]
Avoid scaling if the source & destination region have the same size
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 27 Mar 2012 06:55:23 +0000 (14:55 +0800)]
Check the max resolution supported by hardware when create VA context
It will avoid GPU hang when try to play unsupported large resolution
videos.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
546fdcfa2f4dd162fdd19187255a57272d4f1745)
Conflicts:
src/i965_drv_video.c
src/i965_drv_video.h
Xiang, Haihao [Tue, 27 Mar 2012 06:48:36 +0000 (14:48 +0800)]
Allocate internal buffers with right size for SNB & IVB
The size is scalable with frame width or height
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a97985da277cd48302cfcb0374604874fc77ef7d)
Xiang, Haihao [Mon, 26 Mar 2012 06:12:27 +0000 (14:12 +0800)]
Avoid moving objects in a heap to a new address when expanding this heap
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
ef5efefaec8b3a4eafde2347b98a973f73745421)
Xiang, Haihao [Thu, 22 Mar 2012 01:31:05 +0000 (09:31 +0800)]
Use AVS kernel to implement normal scaling on Sandybridge
Set parameter nlas to 0 to disable NLAS
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
0b38176cda6047b05cf0eacd913f57ce501f4fdf)
Xiang, Haihao [Tue, 20 Mar 2012 01:47:26 +0000 (09:47 +0800)]
Remove weave method
The surface has been weaved for field coded picture.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 20 Mar 2012 01:09:46 +0000 (09:09 +0800)]
Fix the mapping of filter
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 16 Mar 2012 05:29:02 +0000 (13:29 +0800)]
Fix compiler error after merge
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 16 Mar 2012 05:28:01 +0000 (13:28 +0800)]
Merge branch 'vaapi-ext' into staging-work
Conflicts:
src/gen6_mfc.c
Xiang, Haihao [Fri, 16 Mar 2012 05:00:02 +0000 (13:00 +0800)]
Fix VME output offset issue
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 16 Mar 2012 01:26:03 +0000 (09:26 +0800)]
Always append MI_BATCH_BUFFER_END at the end of a batchbuffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 16 Mar 2012 00:48:06 +0000 (08:48 +0800)]
More space for the header of picture & slice in the MFC batchbuffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 15 Mar 2012 06:46:32 +0000 (14:46 +0800)]
MFC: optimize the MFC batchbuffer shader
Xiang, Haihao [Thu, 15 Mar 2012 06:05:48 +0000 (14:05 +0800)]
VME: dual start and adaptive search
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 15 Mar 2012 01:46:37 +0000 (09:46 +0800)]
VME: Handle multiple macroblocks in a single thread
In addition, merge include files for GEN6 & GEN7
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 13 Mar 2012 00:47:44 +0000 (08:47 +0800)]
Merge branch 'vaapi-ext' into staging-work
Conflicts:
src/gen6_mfc.c
src/gen6_vme.c
src/gen7_mfc.c
src/gen7_mfc.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 9 Mar 2012 00:35:32 +0000 (08:35 +0800)]
Setup pipeline to create MFC batchbuffer on Sandybridge
Also clean up the source
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 8 Mar 2012 05:00:35 +0000 (13:00 +0800)]
Setup pipeline to create MFC batchbuffer on IVB
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 8 Mar 2012 04:58:37 +0000 (12:58 +0800)]
New shader for MFC batchbuffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 2 Mar 2012 07:40:51 +0000 (15:40 +0800)]
Add two helper functions for batchbuffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
teaonly [Fri, 2 Mar 2012 06:49:44 +0000 (14:49 +0800)]
Synced gen7 with gen6 for HRD.
teaonly [Fri, 2 Mar 2012 06:41:44 +0000 (14:41 +0800)]
Synced gen7 with gen6 for HRD.
Xiang, Haihao [Thu, 1 Mar 2012 05:17:54 +0000 (13:17 +0800)]
Fix the issue of vaGetImage()/vaPutImage() in multi-threads
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
0b60832061988c68e6a531e6852f02f6308d349c)
Xiang, Haihao [Thu, 1 Mar 2012 04:57:21 +0000 (12:57 +0800)]
Fix map/unmap mismatches
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
918f26fc0c5c38fb8c1002dd48c857897931c5d5)
Xiang, Haihao [Wed, 29 Feb 2012 07:59:46 +0000 (15:59 +0800)]
Fixed VME result offset issue for IVB.
Signe-off-by: Zhou Chang <chang.zhou@intel.com>
Signe-off-by: Xiang, Haihao <haihao.xiang@intel.com
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
18ffbe2b8adcafa62635efa84673d0f09f8278e2)
Xiang, Haihao [Wed, 29 Feb 2012 07:45:07 +0000 (15:45 +0800)]
Preprocess VME shader first
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
65f644f71422f38064677f2fed6e11ac04037936)
Zhou,Chang [Wed, 29 Feb 2012 05:54:52 +0000 (13:54 +0800)]
Fixed multipul slices issue, change end of coded buffer judge.
(cherry picked from commit
5da90f4cc14e24d6b0f2e1c69505b8bfa939b4cd)
Xiang, Haihao [Tue, 28 Feb 2012 03:19:10 +0000 (11:19 +0800)]
Fix memory leak
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
814424d03c88cd7aff57e886587a131f6bf8197f)
Xiang, Haihao [Thu, 1 Mar 2012 05:17:54 +0000 (13:17 +0800)]
Fix the issue of vaGetImage()/vaPutImage() in multi-threads
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
projects / platform / upstream / libva-intel-driver.git / log