Andre Przywara [Wed, 5 May 2021 10:33:40 +0000 (11:33 +0100)]
mmc: sunxi: Increase MMIO FIFO read performance
To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.
However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).
As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.
To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.
We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.
This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 May 2021 09:06:24 +0000 (10:06 +0100)]
mmc: sunxi: Cleanup and fix self-calibration code
Newer SoCs have a self calibration feature, which avoids us writing hard
coded phase delay values into the controller.
Consolidate the code by avoiding unnecessary #ifdefs, and also enabling
the feature for all those newer SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 May 2021 09:04:41 +0000 (10:04 +0100)]
mmc: sunxi: Enable "new timing mode" on all new SoCs
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so
called "new timing mode", so enable this in Kconfig for those SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 May 2021 08:57:47 +0000 (09:57 +0100)]
mmc: sunxi: Cleanup "new timing mode" selection
Among the SoCs using the "new timing mode", only the A83T needs to
explicitly switch to that mode.
By just defining the symbol for that one odd A83T bit to 0 for any other
SoCs, we can always OR that in, and save the confusing nested #ifdefs.
Clean up the also confusing new_mode setting on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Andre Przywara [Wed, 5 May 2021 08:57:47 +0000 (09:57 +0100)]
mmc: sunxi: Fix MMC clock parent selection
Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.
Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.
Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 29 Apr 2021 08:31:58 +0000 (09:31 +0100)]
mmc: sunxi: Fix warnings with CONFIG_PHYS_64BIT
When enabling PHYS_64BIT on 32-bit platforms, we get two warnings about
pointer casts in sunxi_mmc.c. Those are related to MMIO addresses, which
are always below 1GB on all Allwinner SoCs, so there is no problem with
anything having more than 32 bits.
Add the proper casts to make it compile cleanly.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Andre Przywara [Fri, 18 Dec 2020 22:02:11 +0000 (22:02 +0000)]
mmc: sunxi: Avoid #ifdefs in delay and width setup
The delay and bus-width setup are slightly different across the
Allwinner SoC generations, and we covered this so far with some
preprocessor conditionals.
Use the more readable IS_ENABLE() instead.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Andre Przywara [Wed, 28 Apr 2021 20:29:55 +0000 (21:29 +0100)]
sunxi: H616: Enable full 4GB of DRAM
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
As not all devices are actually capable of dealing with more than 32
bits (the DMA in the EMAC for instance), we also limit U-Boot's own
DRAM usage to 4GB on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 25 Apr 2021 23:38:04 +0000 (00:38 +0100)]
sunxi: board: Add H616 MMC2 pins
We hardcode the pinctrl setting for the MMC controllers in boards.c,
since we need them also in the SPL, where there is no DT yet.
Add the respective setting for the H616 SoC, to enable eMMC on boards
with this SoC as well.
Also to make diagnosing this problem easier, print a warning if a board
tries to setup MMC2 pins without a respective SoC setting being defined.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec at siol.net>
Yu-Tung Chang [Sat, 19 Jun 2021 08:16:45 +0000 (16:16 +0800)]
sunxi: h3: Add initial ZeroPi support
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by: Yu-Tung Chang <mtwget@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jernej Skrabec [Mon, 7 Jun 2021 17:42:45 +0000 (19:42 +0200)]
configs: OrangePi PC2: Update defaults
OrangePi PC2 board has DRAM with ODT, so enable it.
H5 SoC is also connected to voltage regulator. It's default value is
reasonable at reset, but might be too low when rebooting with a lower
voltage programmed. In order to avoid instability, enable driver for it
and set it to appropriate voltage.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
[Andre: remove original ZQ value change, adjust commit message]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 May 2021 12:53:05 +0000 (13:53 +0100)]
sunxi: clock: H6/H616: Fix PLL clock factor encodings
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.
This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req
52000000 parent
1176000000 n 2 m 12 rate
49000000
Also the CPU frequency (PLL1) was a tad too high before.
For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Paul Kocialkowski [Thu, 14 Mar 2019 10:38:00 +0000 (10:38 +0000)]
phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
Recent Allwinner platforms (starting with the H3) only use the MUSB
controller for peripheral mode and use HCI for host mode. As a result,
extra steps need to be taken to properly route USB signals to one or
the other. More precisely, the following is required:
* Routing the pins to either HCI/MUSB (controlled by PHY);
* Enabling USB PHY passby in HCI mode (controlled by PMU).
The current code will enable passby for each PHY and reroute PHY0 to
MUSB, which is inconsistent and results in broken USB peripheral support.
Passby on PHY0 must only be enabled when we want to use HCI. Since
host/device mode detection is not available from the PHY code and
because U-Boot does not support changing the mode dynamically anyway,
we can just mux the controller to MUSB if it is enabled and mux it to
HCI otherwise.
This fixes USB peripheral support for platforms with PHY0 dual-route,
especially H3/H5 and V3s.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 25 May 2021 00:20:25 +0000 (01:20 +0100)]
arm: dts: sunxi: h3: Update DT files
Update the H3 DT files from the Linux 5.12 release.
The changes update some boards, and don't affect U-Boot, but fix Gigabit
Ethernet when this DT is passed on to the Linux kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 25 May 2021 00:20:25 +0000 (01:20 +0100)]
arm: dts: sunxi: h5: Update DT files
Update the H5 DT files from the Linux 5.12 release.
The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
this DT is passed on to the Linux kernel. It also introduces DVFS.
This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
that are of no concern to U-Boot.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Tue, 25 May 2021 00:20:25 +0000 (01:20 +0100)]
arm: dts: sunxi: h6: Update DT files
Update the H6 DT files from the Linux 5.12 release.
The changes are minimal (many LED node renames), but also help to enable
USB port 0 in U-Boot (later), enable the RSB device (not yet used in
U-Boot), and also introduce an MMC frequency limit.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Thu, 8 Jul 2021 11:54:35 +0000 (07:54 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 8 Jul 2021 11:50:08 +0000 (07:50 -0400)]
Azure: Remove "spear" jobs
With the spear family of platforms gone, remove references to them from
the build jobs.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 8 Jul 2021 02:55:41 +0000 (22:55 -0400)]
Revert "arm: Remove nsa310s board"
While this platform has not yet been converted, there is active efforts
to do so. Keep the platform for now.
This reverts commit
aa697e6904ba1b3144a46ec642d4695e7c0cdc3e.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 8 Jul 2021 02:50:41 +0000 (22:50 -0400)]
Merge branch '2021-07-07-remove-non-migrated-platforms'
- Remove a large number of platforms that did not migrate to DM_PCI or
DM_USB by 2 years past the migration deadline and do not have a
migration imminent.
Tom Rini [Sat, 22 May 2021 12:47:16 +0000 (08:47 -0400)]
usb: Add correct depends for CMD_USB_MASS_STORAGE
We cannot build this without USB_GADGET_DOWNLOAD support enabled, add
the appropriate depends line.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:15 +0000 (08:47 -0400)]
sniper: Add build guards around MUSB support code
If MUSB support is disabled, these parts of the code will fail to build.
Cc: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:14 +0000 (08:47 -0400)]
arm: Remove spear600 boards and the rest of SPEAr support
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:13 +0000 (08:47 -0400)]
arm: Remove spear320 boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
also the last SPEAR3XX platform, remove that symbol as well.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:12 +0000 (08:47 -0400)]
arm: Remove spear310 boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:11 +0000 (08:47 -0400)]
arm: Remove spear300 boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:10 +0000 (08:47 -0400)]
arm: Remove nsa310s board
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove it
Cc: Gerald Kerma <dreagle@doukki.net>
Cc: Tony Dinh <mibodhi@gmail.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:09 +0000 (08:47 -0400)]
arm: Remove gplugd board
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove it
Cc: Ajay Bhargav <contact@8051projects.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:08 +0000 (08:47 -0400)]
arm: Remove
edb9315a board
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove it.
This is also the last PL010_SERIAL using board, so remove those
references.
Cc: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:07 +0000 (08:47 -0400)]
arm: Remove at91rm9200ek boards
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Andreas Bießmann <andreas@biessmann.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:06 +0000 (08:47 -0400)]
mx6memcal: Disable USB GADGET in SPL
As this board does not use CONFIG_OF_CONTROL and the DM_USB migration
deadline has passed, disable USB_GADGET support.
Cc: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Eric Nelson <eric@nelint.com>
Tom Rini [Sat, 22 May 2021 12:47:05 +0000 (08:47 -0400)]
dockstar: Perform base CONFIG_DM enablement
As these boards support CONFIG_OF_CONTROL today, perform a basic
CONFIG_DM migration.
Cc: Eric Cooper <ecc@cmu.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:04 +0000 (08:47 -0400)]
ib62x0: Perform base CONFIG_DM enablement
As these boards support CONFIG_OF_CONTROL today, perform a basic
CONFIG_DM migration.
Cc: Luka Perkov <luka@openwrt.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:03 +0000 (08:47 -0400)]
iconnect: Perform base CONFIG_DM enablement
As these boards support CONFIG_OF_CONTROL today, perform a basic
CONFIG_DM migration.
Cc: Luka Perkov <luka@openwrt.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:02 +0000 (08:47 -0400)]
pogo_e02: Perform base CONFIG_DM enablement
As these boards support CONFIG_OF_CONTROL today, perform a basic
CONFIG_DM migration.
Cc: Dave Purdy <david.c.purdy@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:01 +0000 (08:47 -0400)]
openrd: Perform base CONFIG_DM enablement
As these boards support CONFIG_OF_CONTROL today, perform a basic
CONFIG_DM migration.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 22 May 2021 12:47:00 +0000 (08:47 -0400)]
snapper9260/snapper9g20: Disable USB
These boards have not converted to DM_USB by the deadline, disable USB
support as they do not enable CONFIG_OF_CONTROL.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:31 +0000 (21:34 -0400)]
configs: Remove unnecessary CONFIG_DM_PCI_COMPAT=y
The following boards no longer need CONFIG_DM_PCI_COMPAT enabled, so
remove that.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sun, 23 May 2021 14:58:05 +0000 (10:58 -0400)]
ppc: Remove T4160RDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_T4160 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:29 +0000 (21:34 -0400)]
ppc: Remove MPC832XEMDS boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:28 +0000 (21:34 -0400)]
ppc: Remove MPC8323ERDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:27 +0000 (21:34 -0400)]
ppc: Remove MPC8315ERDB board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_MPC8315 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:26 +0000 (21:34 -0400)]
ppc: Remove sbc8641d board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. This is also the last
of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 15 May 2021 01:34:25 +0000 (21:34 -0400)]
ppc: Remove xpedite boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this includes
the last ARCH_MPC8572 platform, remove that as well.
Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tom Rini [Sat, 15 May 2021 01:34:24 +0000 (21:34 -0400)]
ppc: Remove kmcoge4 board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:23 +0000 (21:34 -0400)]
ppc: Remove MPC8568MDS board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_MPC8568 platform, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:22 +0000 (21:34 -0400)]
ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
the only ARCH_T1023 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:21 +0000 (21:34 -0400)]
ppc: Remove MPC8555CDS boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this is the only
ARCH_MPC8555 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:20 +0000 (21:34 -0400)]
ppc: Remove MPC8541CDS board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the only
MPC8541 target left, remove that architecture support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:19 +0000 (21:34 -0400)]
ppc: Remove TQM834x board
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:18 +0000 (21:34 -0400)]
ppc: Remove sbc8548 boards
These boards have not been converted to CONFIG_DM_PCI by the deadline and are
also missing conversion to CONFIG_DM. Remove them.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:17 +0000 (21:34 -0400)]
ppc: Remove caddy2 / vme8349 boards
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:16 +0000 (21:34 -0400)]
ppc: Remove MPC8313ERDB boards
These boards have not been converted to CONFIG_DM_PCI by the deadline.
Remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:15 +0000 (21:34 -0400)]
ppc: Remove ve8313 board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tom Rini [Sat, 15 May 2021 01:34:14 +0000 (21:34 -0400)]
ppc: Remove mpc8308_p1m board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Cc: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:13 +0000 (21:34 -0400)]
ppc: Remove many T104x boards
These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or
in some cases CONFIG_DM itself by the deadline. Remove them.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:12 +0000 (21:34 -0400)]
ppc: Remove sbc8349 board
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:10 +0000 (21:34 -0400)]
m68k: Remove M5475x boards
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is the last of the mcf547x_8x family of boards,
remove that support as well.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:09 +0000 (21:34 -0400)]
m68k: Remove M5485 boards
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is all of the CONFIG_M548x platforms as well,
remove that code.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:07 +0000 (21:34 -0400)]
ppc: Drop MPC837XERDB_SLAVE for now
Drop the MPC837XERDB_SLAVE configuration.
Cc: Sinan Akman <sinan@writeme.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 15 May 2021 01:34:06 +0000 (21:34 -0400)]
pci: Remove non-DM board_pci_fixup_dev() declaration
With the ventana boards migrated to DM_PCI and DM_ETH, we can remove
this prototype.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 7 Jul 2021 17:34:42 +0000 (13:34 -0400)]
Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dm
various minor sandbox improvements
Tom Rini [Wed, 7 Jul 2021 17:32:22 +0000 (13:32 -0400)]
Merge branch '2021-07-06-update-to-gcc11-clang11'
- Update CI to use gcc-11.1 and clang-11 to build everything. This
requires a few fixes to the code that these newer compilers have
exposed.
Tom Rini [Wed, 7 Jul 2021 15:34:29 +0000 (11:34 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
Tom Rini [Fri, 2 Jul 2021 14:41:58 +0000 (10:41 -0400)]
Azure/GitLab: Move to gcc-11.1.0 and LLVM-11
- Move to gcc-11.1.0 builds from kernel.org for supported platforms and
LLVM-11 for those tests.
- As Heinrich has noted, the RISC-V platform specification has a profile
OS-A for running rich operating systems like Linux and BSD. This profile
requires 64bit and UEFI conforming to the EBBR. Only the 'embedded'
profile may use 32bit. Given this, drop grub for 32bit RISC-V as it no
longer compiles with gcc-11.1 and upstream is unlikely to fix it:
https://www.mail-archive.com/grub-devel@gnu.org/msg30736.html
- Update to grub-2.06 release to address other issues of building with
gcc-11.1.
- Update to newer Xtensa (gcc-9.2.0) and ARC (gcc-10.2) toolchains
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Rick Chen <rick@andestech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Wed, 7 Jul 2021 07:36:26 +0000 (15:36 +0800)]
x86: Drop _X86EMU_env definition when CONFIG_BIOSEMU is used
With x86 we can execute an option ROM either natively or using the
x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share
the _X86EMU_env variable, with the native code using it to hold
register state during interrupt processing.
At present, in 32-bit U-Boot, the variable is declared twice, once
in common code and once in code only compiled with CONFIG_BIOSEMU.
With GCC 11 this causes a 'multiple definitions' error on boards
with CONFIG_BIOSEMU.
Drop the emulator definition when CONFIG_BIOSEMU is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Mon, 3 May 2021 20:48:58 +0000 (16:48 -0400)]
bootstage: Eliminate when not enabled
When we do not have bootstage enabled, rather than include an empty
dummy function, we just don't reference it. This saves us space in some
tight builds. This also shows a few cases where show_boot_progress was
incorrectly guarded before.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 3 May 2021 20:48:57 +0000 (16:48 -0400)]
Makefile: Disable gcc-10.0 introduced warnings
Follow what the Linux Kernel does here and disable the
'zero-length-bounds', 'array-bounds' and 'stringop-overflow' warnings
here.
This brings in commits
5c45de21a2223,
44720996e2d79 and
5a76021c2eff7
from the Linux Kernel.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 3 May 2021 20:48:56 +0000 (16:48 -0400)]
pinctrl: mscc: Fix multiple definition error
With gcc-11 we get a multiple errors here as the declarations for
mscc_pinctrl_ops and mscc_gpio_ops are missing an extern.
CC: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: Lars Povlsen <lars.povlsen@microchip.com>
Cc: Horatiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tom Rini [Mon, 3 May 2021 20:48:55 +0000 (16:48 -0400)]
eb_cpu5282: Declare diplay_width / display_height as externs
The board code here references the display_width / display_height
variables set in the video driver, declare these as externs as gcc-11
will notice and lead to a multiple definition error.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 3 May 2021 20:48:54 +0000 (16:48 -0400)]
freescale: Drop unnecessary cpld_data_t non-typedef
In some board cpld.h files the definition of the cpld_data struct
not-quite makes a typedef for cpld_data_t. This problem is caught with
gcc-11 as a multiple definition error. As there are no users of this
non-typedef, fix this by not declaring it one to begin with.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 3 May 2021 20:48:53 +0000 (16:48 -0400)]
ARM: mvebu: a38x: Correct mismatched bound warnings
With gcc-11 we see:
drivers/ddr/marvell/a38x/ddr3_debug.c:672:47: error: argument 2 of type 'u32[5]' {aka 'unsigned int[5]'} with mismatched bound [-Werror=array-parameter=]
672 | int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
| ~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from drivers/ddr/marvell/a38x/ddr3_training_ip_engine.h:10,
from drivers/ddr/marvell/a38x/ddr3_init.h:17,
from drivers/ddr/marvell/a38x/ddr3_debug.c:6:
drivers/ddr/marvell/a38x/ddr3_training_ip_flow.h:116:47: note: previously declared as 'u32[]' {aka 'unsigned int[]'}
And similar warnings. Correct these by updating the prototype. Remove
the prototype for ddr3_tip_read_pup_value as it is unused.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Wed, 7 Jul 2021 12:52:14 +0000 (08:52 -0400)]
Merge tag 'u-boot-atmel-fixes-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel fixes for 2021.10 cycle:
This small fixes set is dedicated to fixing the onewire subsystem for
the at91 boards which was broken since 2020.04.
Tianrui Wei [Wed, 7 Jul 2021 07:48:22 +0000 (15:48 +0800)]
riscv: dts: add OpenPiton RISC-V board dts support
Previous device tree for OpenPiton emits a warning during compilation.
This commit fixes the previous warning adds dts to the OpenPiton RISC-V
board and added the device tree to MAINTAINER file.
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Tom Rini [Tue, 6 Jul 2021 22:10:10 +0000 (18:10 -0400)]
Merge branch '2021-07-06-platform-updates'
- mpc8379erdb DM_USB, DM_PCI and DM_ETH support.
- Drop PCI support from the integrator family of boards
- Add synquacer support
- Assorted lpc32xx updates and improvements
- snapdragon (and related) fixes, Broadcom iproc update
Stephan Gerhold [Mon, 28 Jun 2021 08:40:09 +0000 (10:40 +0200)]
serial: serial_msm: Ensure BAM/single character mode are disabled
At the moment, the U-Boot serial_msm driver does not initialize the
UART_DM_DMEN register with the required value. Usually this does not
cause any problems, because there is Qualcomm's LK bootloader running
before U-Boot which initializes the register with the correct value.
It's important that this register is initialized correctly, because
the U-Boot driver does not make use of the BAM/DMA or single character
mode functionality of the UART controller. A different bootloader
before U-Boot might initialize the register differently.
For example, on DragonBoard 410c U-Boot can also be installed to the
"aboot" partition (replacing LK entirely). In this case U-Boot is
loaded directly by SBL, which seems to use the single-character mode
for some reason. In single character mode there is always just one
char in the FIFO, instead of the 4 characters expected by
msm_serial_fetch(). It also causes issues with "earlycon" later in
the Linux kernel, which tries to output 4 chars at once,
but only the first char will be written.
This causes early UART log in Linux to be corrupted like this:
[ 00ano:ameoi .Q1B[ 00ac _idaM00080oo'ahani-lcle._20). 15NdNii 5 SPMSJ20:U2
[ 00rkoolmsamel
[ 00Fw ]elamletopsioble
[ 00ore
instead of
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd030]
[ 0.000000] Machine model: Qualcomm Technologies, Inc. APQ 8016 SBC
[ 0.000000] earlycon: msm_serial_dm0 at MMIO 0x00000000078b0000 (options '')
[ 0.000000] printk: bootconsole [msm_serial_dm0] enabled
Make sure to initialize UART_DM_DMEN correctly to fix this issue
when loading U-Boot directly after SBL (instead of through LK).
There is no functional difference when loading U-Boot through LK
since LK also initializes UART_DM_DMEN to 0x0. [1]
[1]: https://git.linaro.org/landing-teams/working/qualcomm/lk.git/tree/platform/msm_shared/uart_dm.c?h=dragonboard410c-LA.BR.1.2.7-03810-8x16.0-linaro3#n203
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Stephan Gerhold [Sun, 27 Jun 2021 11:06:15 +0000 (13:06 +0200)]
arm: dts: db410c: Add missing cd-gpios for SD card detection
It looks like SD card detection is broken at the moment for DB410c.
The eMMC is detected correctly, but the SD card is not.
This is probably similar to the issue fixed in commit
850514740358
("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC,
except that the SD card does not have a property like "non-removable"
that skips the card detection.
The SDHCI on DB410c cannot detect itself if a SD card is inserted,
so add the necessary cd-gpios to make SD card detection work again.
While at it, fix the #gpio-cells for the soc_gpios to avoid DTC
warnings - the soc_gpios are actually already used with two cells
for the gpio-leds so this was just wrong all the time.
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Sheep Sun [Sun, 20 Jun 2021 02:34:35 +0000 (10:34 +0800)]
arm: snapdragon: Fix typo in clk_bcr_update()
Fix typo in clock-snapdragon.c
Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
Sheep Sun [Sun, 20 Jun 2021 02:34:34 +0000 (10:34 +0800)]
arm: snapdragon: Use correct GICC register on APQ8016
The GICC register used by u-boot is 0x0a20c000, which is actually a GICC
for WCNSS, the WLAN processor. U-boot runs on the Application Processor,
therefore it should use APCS GICC instead. Hence, correct it with APCS GICC
register address.
Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:09 +0000 (22:37 -0400)]
lpc32xx: ea-lpc3250devkitv2: enable i2c (DM)
Enable a DMed i2c driver for the ea-lpc3250devkitv2 board.
Include some sample commands/output for testing.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:08 +0000 (22:37 -0400)]
Kconfig: convert CONFIG_SYS_I2C_LPC32XX
Convert the CONFIG_SYS_I2C_LPC32XX configuration symbol from an include
directive to a Kconfig value.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Trevor Woerner [Fri, 11 Jun 2021 02:37:07 +0000 (22:37 -0400)]
lpc32xx: i2c: finish DM/OF code
Add the of_match/compatible string to the lpc32xx i2c driver so it works
correctly with device-tree.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:06 +0000 (22:37 -0400)]
lpc32xx: i2c: fix base address
The lpc32xx driver was not obtaining the per-device base address correctly
from the device tree. Fix the FIXME in order to get the correct base address.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:05 +0000 (22:37 -0400)]
lpc32xx: i2c: remove unused define
The LPC32XX_I2C_STAT_DRMI is not used anywhere so remove it.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:04 +0000 (22:37 -0400)]
arm: lpc32xx: add EA LPC3250 DevKitv2 board support
Add basic support for running U-Boot on the Embedded Artists LPC3250
Developer's Kit v2 board by launching U-Boot from the board's s1l loader
(which comes pre-installed on the board).
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:03 +0000 (22:37 -0400)]
lpc32xx: import device tree from Linux
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board
directly and unmodified from the latest Linux kernel.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Trevor Woerner [Fri, 11 Jun 2021 02:37:02 +0000 (22:37 -0400)]
lpc32xx: Kconfig: switch to CONFIG_CONS_INDEX
There's nothing special or unique to the lpc32xx that requires its own config
parameter for specifying the console uart index. Therefore instead of using
the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
already-available CONFIG_CONS_INDEX from Kconfig.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:45:31 +0000 (18:45 +0900)]
configs: synquacer: Enable EFI capsule update support
Enable EFI capsule update support. With the EFI capsule update,
you can update U-Boot, TF-A and OP-TEE. TF-A and OP-TEE are
usually combined as a FIP binary, but if the binary is bigger
than 480KB, you have to modify FIP header, split the OP-TEE
and stores the OP-TEE binary in the different place. This
configuration supports both cases.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:45:21 +0000 (18:45 +0900)]
doc: qemu: arm64: Fix the documentation of capsule update
Since the EDK2 GenerateCapsule script is out of date and it
doesn't generate the supported version capsule file, the document
should refer the mkeficapsule in tools.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:45:10 +0000 (18:45 +0900)]
board: synquacer: Add DeveloperBox 96boards EE support
Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.
For more information, see this page;
https://www.96boards.org/product/developerbox/
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:44:59 +0000 (18:44 +0900)]
ARM: dts: synquacer: Add device trees for DeveloperBox
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit
83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Jassi Brar [Fri, 4 Jun 2021 09:44:48 +0000 (18:44 +0900)]
i2c: synquacer: SNI Synquacer I2C controller
Add driver for class of I2C controllers found on
Socionext Synquacer platform.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Jassi Brar [Fri, 4 Jun 2021 09:44:27 +0000 (18:44 +0900)]
spi: synquacer: Add HSSPI SPI controller driver for SynQuacer
This is a driver for the HSSPI SPI controller on SynQuacer SoC.
The HSSPI has command sequence mode (memory mapped) and
direct mode (FIFO access). The driver will operate it under
the direct mode. And before booting OS, it switch back to the
command sequence mode since that is compatible with default
EDK2 behavior.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Jassi Brar [Fri, 4 Jun 2021 09:44:16 +0000 (18:44 +0900)]
mmc: synquacer: Add SynQuacer F_SDH30 SDHCI driver
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Masami Hiramatsu [Fri, 4 Jun 2021 09:44:06 +0000 (18:44 +0900)]
pci: synquacer: Add SynQuacer ECAM based PCIe driver
Add ECAM based SynQuacer PCIe RC driver. This driver configures the
PCIe RC and filter out a ghost pcie config.
Since the Linux kernel expects "socionext,synquacer-pcie-ecam" device
is configured by firmware (EDK2), it doesn't re-configure in the kernel.
So as same as EDK2, U-Boot needs to configure it before boot the kernel.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:43:55 +0000 (18:43 +0900)]
gpio: Introduce CONFIG_GPIO_EXTRA_HEADER to cleanup #ifdefs
Since some SoCs and boards do not hae extra asm/arch/gpio.h,
introduce CONFIG_GPIO_EXTRA_HEADER instead of adding
!define(CONFIG_ARCH_XXXX) in asm/gpio.h.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:43:34 +0000 (18:43 +0900)]
dm: pci: Skip setting VGA bridge bits if parent device is the host bus
Commit
bbbcb5262839 ("dm: pci: Enable VGA address forwarding on bridges")
sets the VGA bridge bits by checking pplat->class, but if the parent
device is the pci host bus device, it can be skipped. Moreover, it
shouldn't access the pplat because the parent has different plat data.
Without this fix, "pci enum" command cause a synchronous abort.
pci_auto_config_devices: start
PCI Autoconfig: Bus Memory region: [
78000000-
7fffffff],
Physical Memory [
78000000-7fffffffx]
PCI Autoconfig: Bus I/O region: [0-ffff],
Physical Memory [
77f00000-77f0ffffx]
pci_auto_config_devices: device pci_6:0.0
PCI Autoconfig: BAR 0, Mem, size=0x1000000, address=0x78000000 bus_lower=0x79000000
PCI Autoconfig: BAR 1, Mem, size=0x8000000, No room in resource, avail start=
79000000 / size=8000000, need=8000000
PCI: Failed autoconfig bar 14
PCI Autoconfig: BAR 2, I/O, size=0x4, address=0x1000 bus_lower=0x1004
PCI Autoconfig: BAR 3, Mem, size=0x2000000, address=0x7a000000 bus_lower=0x7c000000
PCI Autoconfig: BAR 4, I/O, size=0x80, address=0x1080 bus_lower=0x1100
PCI Autoconfig: ROM, size=0x80000, address=0x7c000000 bus_lower=0x7c080000
"Synchronous Abort" handler, esr 0x96000006
elr:
00000000e002bd28 lr :
00000000e002bce8 (reloc)
elr:
00000000fff6fd28 lr :
00000000fff6fce8
x0 :
0000000000001041 x1 :
000000000000003e
x2 :
00000000ffb0f8c8 x3 :
0000000000000001
x4 :
0000000000000080 x5 :
0000000000000000
x6 :
00000000fff718fc x7 :
000000000000000f
x8 :
00000000ffb0f238 x9 :
0000000000000008
x10:
0000000000000000 x11:
0000000000000010
x12:
0000000000000006 x13:
000000000001869f
x14:
00000000ffb0fcd0 x15:
0000000000000020
x16:
00000000fff71cc4 x17:
0000000000000000
x18:
00000000ffb13d90 x19:
00000000ffb14320
x20:
0000000000000000 x21:
00000000ffb14090
x22:
00000000ffb0f8c8 x23:
0000000000000001
x24:
00000000ffb14c10 x25:
0000000000000000
x26:
0000000000000000 x27:
0000000000000000
x28:
00000000ffb14c70 x29:
00000000ffb0f830
Code:
52800843 52800061 52800e00 97ffcf65 (
b9400280)
Resetting CPU ...
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Masami Hiramatsu [Fri, 4 Jun 2021 09:43:23 +0000 (18:43 +0900)]
ata: ahci-pci: Use scsi_ops to initialize ops
Without this fix, scsi-scan will cause a synchronous abort
when accessing ops->scan.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chris Packham [Fri, 4 Jun 2021 02:25:36 +0000 (14:25 +1200)]
arm: iproc: Add higher speed configurations
Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on
equivalent code in Broadcom's LDK 5.0.6.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Linus Walleij [Sat, 15 May 2021 12:44:19 +0000 (14:44 +0200)]
ARM: integrator: Drop PCI support
We didn't convert the Integrator to use DM for PCI in
time, and we don't use it either so let's just drop
PCI support from the Integrator.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>