aco/gfx11: fix get_gfx11_true16_mask with v_cmp_class_f16

The second operand is 16bit, so the we need to use VOP3 to address v128-v255.

Closes: #9413
Fixes: 6872f8d861b ("aco/gfx11: allow true 16-bit instructions to access v128+")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24294>

nir/tests: add nir_opt_dead_cf_test.jump_before_constant_if

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24235>

nir/opt_dead_cf: remove nodes after a jump earlier

In the case of:
   halt
   // succs: b9
   if %618 {
       block b3:// preds:
       break
       // succs: b6
   } else {
       block b4:  // preds: , succs: b5
   }
   block b5:    // preds: b4
   32    %556 = iadd %617, %2 (0x1)
opt_constant_if() doesn't work because stitch_blocks() can't join blocks if the
before ends in a jump and the after isn't empty.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24235>

nir/tests: Use a single binary

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24249>

nir/tests: Refactor boilerplate into a common header

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24249>

tu,freedreno: Forbid blit event for R8G8_SRGB due to gpu faults

Same cause as for other R8G8 formats - msaa resolve via
blit event causes gpu fault.

Fixes:
 dEQP-VK.api.image_clearing.*.clear_color_attachment.*.r8g8_srgb_*

Fixes: 029919f3c83f379065515708188d5c439c3fa6bc
("tu: allow using resolve engine for SRGB MSAA resolves")

Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24277>

panvk: Use 1.0 in ICD Manifest json

PanVK downgraded from supporting Vulkan 1.1 to 1.0, but did not change
their ICD Manifest api_version to reflect that. This cause the Vulkan-Loader
to interpret the ICD as a 1.1 driver erroneously. Originally discussed in this
issue https://github.com/KhronosGroup/Vulkan-Loader/issues/1242

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24289>

intel/compiler: load debug mesh compaction options once

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20407>

intel/compiler,anv: put some vertex and primitive data in headers

Both per-primitive and per-vertex space is allocated in MUE in 8 dword
chunks and those 8-dword chunks (granularity of
3DSTATE_SBE_MESH.Per[Primitive|Vertex]URBEntryOutputReadLength)
are passed to fragment shaders as inputs (either non-interpolated
for per-primitive and flat vertex attributes or interpolated
for non-flat vertex attributes).

Some attributes have a special meaning and must be placed in separate
8/16-dword slot called Primitive Header or Vertex Header.

Primitive Header contains 4 such attributes (Cull Primitive,
ViewportIndex, RTAIndex, CPS), leaving 4 dwords (the rest of 8-dword
slot) potentially unused.

Vertex Header is similar - it starts with 3 unused dwords, 1 dword for
Point Size (but if we declare that shader doesn't produce Point Size
then we can reuse it), followed by 4 dwords for Position and optionally
8 dwords for clip distances.

This means we have an interesting optimization problem - we can put
some user attributes into holes in Primitive and Vertex Headers, which
may lead to smaller MUE size and potentially more mesh threads running
in parallel, but we have to be careful to use those holes only when
we need it, otherwise we could force HW to pass too much data to
fragment shader.

Example 1:
Let's assume that Primitive Header is enabled and user defined
12 dwords of per-primitive attributes.

Without packing we would consume 8 + ALIGN(12, 8) = 24 dwords of
MUE space and pass ALIGN(12, 8) = 16 dwords to fragment shader.

With packing, we'll consume 4 + 4 + ALIGN(12 - 4, 8) = 16 dwords of
MUE space and pass ALIGN(4, 8) + ALIGN(12 - 4, 8) = 16 dwords to
fragment shader.

16/16 is better than 24/16, so packing makes sense.

Example 2:
Now let's assume that Primitive Header is enabled and user defined
16 dwords of per-primitive attributes.

Without packing we would consume 8 + ALIGN(16, 8) = 24 dwords of
MUE space and pass ALIGN(16, 16) = 16 dwords to fragment shader.

With packing, we'll consume 4 + 4 + ALIGN(16 - 4, 8) = 24 dwords of
MUE space and pass ALIGN(4, 8) + ALIGN(16 - 4, 8) = 24 dwords to
fragment shader.

24/24 is worse than 24/16, so packing doesn't make sense.

This change doesn't affect vk_meshlet_cadscene in default configuration,
but it speeds it up by up to 25% with "-extraattributes N", where
N is some small value divisible by 2 (by default N == 1) and we
are bound by URB size.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20407>

intel/compiler/mesh: compactify MUE layout

Instead of using 4 dwords for each output slot, use only the amount
of memory actually needed by each variable.

There are some complications from this "obvious" idea:
- flat and non-flat variables can't be merged into the same vec4 slot,
  because flat inputs mask has vec4 stride
- multi-slot variables can have different layout:
   float[N] requires N 1-dword slots, but
   i64vec3 requires 1 fully occupied 4-dword slot followed by 2-dword slot
- some output variables occur both in single-channel/component split
  and combined variants
- crossing vec4 boundary requires generating more writes, so avoiding them
  if possible is beneficial

This patch fixes some issues with arrays in per-vertex and per-primitive data
(func.mesh.ext.outputs.*.indirect_array.q0 in crucible)
and by reduction in single MUE size it allows spawning more threads at
the same time.

Note: this patch doesn't improve vk_meshlet_cadscene performance because
default layout is already optimal enough.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20407>

radv: add radv_compile_cs() to compile a compute shader

This doesn't rely on the pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24280>

radv: stop using an array of binaries when compiling a compute shader

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24280>

Revert "intel/ci: disable iris-jsl-deqp because it always fails for an AMD MR"

This reverts commit da4b5b4a47ca727a7c8892d2bea50739df3b94ed.

Signed-off-by: Zhang Ning <zhangn1985@outlook.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23815>

nir/opt_copy_prop_vars: drop reuse of dynamic arrays

After the previous commit there are so few to reuse that this is no
longer worth doing and actually causes compilation to slow down.

The Blender shader compile time in issue #9326 improves as folows:
21.11 seconds -> 9.90 seconds

The CTS test dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20
improves as follows:

0.92 seconds -> 0.68 seconds

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9326

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24227>

nir/opt_copy_prop_vars: skip cloning of copies arrays until needed

Most of the variables in the hash table will never actually be looked up
for any given block so cloning every possible value just creates a bunch
of unrequired memcpy calls.

Here we change the code to only clone the copies array once it is
actually looked up for the first time.

The Blender shader compile time in issue #9326 improves as folows:
151.09 seconds -> 21.11 seconds

The CTS test dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20
improves as follows:

1.67 seconds -> 0.92 seconds

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24227>

nir/opt_copy_prop_vars: remove var hash entry on kill alias

If kill alias results in the hash table entry holding an empty
copies array then remove the hash entry and return the dynamic array
to the unused pool.

This helps avoid hash table size getting out of control in very large
shaders.

151.09 seconds -> 118.60 seconds

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24227>

nir/opt_copy_prop_vars: speedup cloning of copy tables

Here we change things to simply clone the entire hash table. This
is much faster than trying to rebuild it and is needed to avoid
slow compilation of very large shaders.

The Blender shader compile time in issue #9326 improves as folows:
251.29 seconds -> 151.09 seconds

The CTS test dEQP-GLES31.functional.ubo.random.all_per_block_buffers.20
improves as follows:

2.38 seconds -> 1.67 seconds

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24227>

nir/opt_copy_prop_vars: don't clone copies if branch empty

There is no point doing an expensive clone of the copies if the
if-branch is empty.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24227>

radeonsi: enable aco compile for mono merged ES/GS

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: enable aco compile for mono merged LS/HS

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: calculate lds size for merged shaders

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: aco compile support merged mono shader

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: refine si_llvm_es_build_end

1. merge si_set_es_return_value_for_gs into si_llvm_es_build_end
2. stop return value when mono mode in which case GS use ES input as
   input instead of ES output

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: refine si_llvm_ls_build_end

1. merge si_set_ls_return_value_for_tcs into si_llvm_ls_build_end because they
   do the same job to return value
2. stop return value when mono mode with different thread count, in which case
   TCS use LS input as its input instead of LS output
3. use si_insert_input_ret_float

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: remove param type check in wrapper function

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: move vertex shader vb desc input sgpr args to last

ACO use same args for merged shader stages, but vb desc input sgpr args
is not present when second stage of merged shader. In order to share
same shaders args, move it to last so other args have same index.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: simplify si_build_wrapper_function

We only need it to merge LS/HS or ES/GS now, prolog and epilog have
been lowered in nir already. So we just need to handle two parts and
they are sure to be first and second stage of a merged shader.

This also remove the needs SGPRs must be before VGPRs, which is required
by following commits to move some SGPRs after VGPRs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: init aco shader info for merged LS/HS

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: extract si_get_prev_stage_nir_shader to be shared with aco

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

radeonsi: aco does not pass LS outputs to HS by arg

aco has global input/output variables for this.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

aco,radv: replace tess_input_vertices shader info param

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24204>

ci/freedreno: cover all texture gather flakes

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24300>

llvmpipe: Fix compiling with LP_USE_TEXTURE_CACHE

Fixes: 36eb75d ("llvmpipe: move to common sampler/image binding code")
Closes: #9359

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24243>

nir: Fix 16-component nir_replicate.

Fixes: f534c2c539f ("nir/builder: Add nir_replicate helper")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24286>

aco: Fix some constant patterns in 16-bit vec4 construction with s_pack.

Fixes: 04e3d7ad930 ("aco: improve nir_op_vec with constant operands")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24286>

aco: fix nir_op_vec8/16 with 16-bit elements.

Fixes: 5718347c2b4 ("aco: implement vec2/3/4 with subdword operands")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24286>

asahi: Don't depend on glibc to decode

fopencookie is a glibc feature, so we can't use it on macOS (and
probably other libc's?). It's only used for the hypervisor interface,
though, so we can just make the hypervisor piece glibc-only while
otherwise fixing the wrap.dylib build.

Fixes: ee83453f69f ("asahi: Add a shared library interface for decode")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24293>

asahi: drop unused include paths

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24287>

ci/etnaviv: update ci expectations

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24291>

amd/ci: update radv-stoney-aco-fails.txt for depth/stencil resolve

image_2d_16_64_6 ones have been fixed by the previous commit.  The
others are outdated.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23959>

radv: disable tc-compat htile for layered images on gfx8

sliceInterleaved may be true for layered images on gfx8.  Such a htile
cannot be cleared with radv_clear_htile.

Fixes 24 failures in
dEQP-VK.renderpass2.depth_stencil_resolve.image_2d_16_64_6.* on GFX8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23959>

tgsi: drop two unused functions

Removes:
* tgsi_util_get_src_from_ind
* tgsi_full_src_register_from_dst

The last usage of these got removed in !24175

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24283>

venus: use in_render_pass to skip present_src counting

It's an early return also benefiting dynamic rendering. We then no
longer need to track the legacy pass from inheritance info.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: refactor more cmd states into cmd builder

This change:
- adds helpers for cmd begin/end rendering
- simplifies cmd reset
- updates ordering to align with cmd builder

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: avoid redundant tracking of render pass

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: add helpers to track subpass view mask

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: cleanup vn_cmd_begin_render_pass usage

For secondary command buffers, vn_cmd_begin_render_pass was only used to
track inherited render pass previously. So we clean it up.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: use tracked queue_family_index from the cmd pool

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: remove redundant fb tracking from cmd builder

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: move transient storage from cmd to pool

The storage is for command scope usage, so it fits better for the pool.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: log and doc the broken query feedback in suspended render pass

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: fix cmd state leak across implicit reset

Reset cmd states during vkBeginCommandBuffer regardless of the
VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT for simplicity.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

venus: fix a cmd builder render_pass state leak across reset

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24103>

gallivm: fix atomic global temporary storage.

Fixes regression on llvm15 with
piglit tests/cl/program/execute/builtin/atomic/atomic_xchg-global.cl

Fixes: f28129000511 ("gallivm: Fix atomic_global types")
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24267>

svga: set clear_texture to NULL for vgpu9

With PIPE_CAP_CLEAR_TEXTURE removed, we need to set clear_texture to NULL
on svga vgpu9 device so it can use the fallback path.

Fixes: a1eabeff660 ("gallium: remove PIPE_CAP_CLEAR_TEXTURE")

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24264>

ci/venus: update venus-lavapipe expectations

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24263>

lvp: avoid reading immutable sampler from desc write info

Lavapipe has switched to layer push descriptor support atop descriptor
updates internally since 12a7fc51c77925a5562fd104a8fbd664a46ffc8b, so
it must skip retrieving immutable samplers from the write info even if
the update call itself is blessed by the spec to not hit that case.

Fixes: 12a7fc51c77 ("lavapipe: Rework descriptor handling")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24263>

vulkan: bump header register to 1.3.258

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24279>

tu, freedreno/a6xx: Remove has_ccu_flush_bug

Based on the previous commit, this isn't actually a bug and is expected
behavior. Turnip should already be handling it correctly for user
flushes, we just have to make sure to handle it for flushes we insert
ourselves in turnip and freedreno.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>

tu: Fix and simplify execution dependency handling

When I wrote this code, I was under the impression that at most one
context from each cluster could be executing at a time. This would mean
that we could treat clusters as pipeline stages and only insert a WFI if
there was a bubble where an earlier stage depends on the result of a
later stage.

This mental model was wrong, though. Experiments on a6xx show it's
possible for two contexts to be executing simultaneously, even though
there are only two contexts - register writing is just stalled until the
earliest-launched context finishes.

This means that the mental model is now much simpler. Any draw can, in
theory, execute in parallel with any previous draw, blit, flush, etc,
although it seems that flushes do wait for any earlier work to finish.
Clusters are mostly just an implementation detail that only matter in
some corner cases, like setting a non-context register (written in the
last cluster) that is used by an earlier cluster that can race ahead of
the write.

An example where this makes a difference is a fragment shader that
writes an image via stib followed by a blit from that same image.
Because both operations happen in the same cluster and use the same
cache, we wouldn't emit anything in the barrier, however actually we
still need to WFI.

This was getting worse on a7xx because later clusters now have 4
contexts, making it easier for draws to be executed in parallel. However
AFAICT it was already a problem on a6xx.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>

tu: Fix vk2tu_*_stage flag type

New flags were silently getting dropped.

Fixes: 59259a01671 ("tu: Convert to sync2 entrypoints")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24162>

docs: update calendar for 23.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24281>

docs: add sha256sum for 23.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24281>

docs: add release notes for 23.1.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24281>

gallium/auxiliary/vl: Fix RGB->YCbCr full range matrix

Also rename it to bt_709_rev_full as there already
is bt_709 which is used for YCbCr->RGB.

Fixes: 8a21efce3a2 ("frontends/va: Add postproc support for converting to full range")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24238>

radeonsi/vcn: num bs_bufs must be proportional to num jpeg engines

using limited number of bs buffers constraints the simultaneous
use of all available jpeg engines especially when count is lesser than
that of the available engines. make sure the number of buffers
available are more than or equal to the number of jpeg engines on the asic.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24240>

radeonsi/vcn: support variable number of bs_bufs

add support to use variable number of bitstream buffers for decode

v2: remove the always true if condition (CI report)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24240>

radv: bind the pre-compiled PS epilog to the cmdbuf state

For PS epilogs we have two paths, the first one is to pre-compile PS
epilogs at pipeline creation time, while the second one is to compile
PS epilogs on-demand when some dynamic states are used.

Binding the pre-compiled PS epilog to the cmdbuf state allows us to
remove one more pipeline dependency when recording cmdbufs (for shader
objects).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24254>

radv: pass a shaders array for computing ia_multi_vgt_param

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24251>

radv: remove unused param in radv_pipeline_emit_vgt_gs_out()

Also rename the function.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24251>

radv: stop using a pipeline for emitting VGT_VERTEX_REUSE_BLOCK_CNTL

Passing a TES is enough.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24251>

nir: Remove register arrays

Nothing produces them any more, so remove them from NIR. This massively reduces
the size of nir_src, which should improve performance all over.

nir_src size reduced from 56 bytes -> 40 bytes (pahole results on arm64, x86_64
should be similar.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>

nir: Rename lower_locals_to_reg_intrinsics back

The short name is freed up.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>

nir: Remove nir_lower_locals_to_regs

No more users, all switched to the intrinsic version.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>

panfrost: Remove unused helpers

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>

intel/fs: Don't read reg.base_offset

It's not set in the new intrinsics path.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24253>

anv: drop CFE state validation checks

anv no longer needs to track if the CFE state is valid since we ensure
that the state is valid at pipeline creation time.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23934>

anv,iris: program the maximum number of threads on compute queue init

Fixes: 90a39cac87 ("intel/blorp: Emit compute program based on BLORP_BATCH_USE_COMPUTE")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23934>

etnaviv: nir: lower nir_texop_txs

Non of the GPU models know at this time have hardware support to
retrieve the dimensions of a level of a texture. Do almost the
same as the binary blob and store the needed values as uniforms.

Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>

etnaviv: nir: support intrinsic used for txs lowering

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>

nir: add enta specific intrinsic used for txs lowering

Non of the know etnaviv GPUs support this feature in hardware
and the binary blob provides sizes via uniforms too.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>

etnaviv: move nir texture lowerings into one pass

This is just a prep commit to keep all texture related
lowerings in one c file.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>

anv: merge cases leading to the same code

Added in: 688968e8880 ("anv: add support for direct descriptor in allocation/writes")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>

anv: drop unused function

Added in: 02cecffe2bb ("anv: add a pass to partially lower resource_intel")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>

intel/compiler: remove redundant code

has_lsc is checked few lines above, so this code doesn't matter.

Added in: a358b97c586 ("intel/fs: optimize uniform SSBO & shared loads")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>

anv: use ycbcr_info for P010 format

Since !24096 landed, we can just use ycbcr_info to get information
of an image of the P010 format.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24265>

nouveau: Delete the nouveau_compiler tool

It's TGSI only.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop BuildUtil::Location

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop BuildUtil::DataArray

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop ConverterCommon::Subroutine

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Drop tgsi support from nv50_ir_prog_info

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nouveau: Delete nv50_ir_from_tgsi.cpp

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nv50: Keep nir directly in nv50_program

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

nvc0: Keep nir directly in nvc0_program

instead of under pipe_shader_state.

This makes it obvious that we never produce tgsi shaders since
c3cbe610 "nouveau: Delete the NV50_PROG_USE_TGSI env var."

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>

zink: emit SpvCapabilitySampleMaskPostDepthCoverage with SpvExecutionModePostDepthCoverage

can't have one without the other

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24183>

zink: be even dumber about buffer refs when replacing storage

these extra checks can cause issues when multiple contexts and transfer
ops are involved

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24141>

nvc0: fix num_gprs for Volta+

Overallocating by 2 gprs for ugprs is a wild guess by me. It does make
sense though as each subgroup shares 64 ugprs and that's 2 per thread.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24261>

llvmpipe: enable system SVM

The API bits are already implemented in clover and rusticl and by
definition a CPU driver implements SVM.

This should allow anybody to work on proper SyCL/CHIP-SPV support for
rusticl running llvmpipe.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>

rusticl/mesa: make svm_migrate optional

It's just a hint and drivers might want to ignore implementing it for now.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>

intel/isl: Add a score for DG2_RC_CCS

This enables the DG2 render compression modifier in anv. When I tested
this against vkcube, I observed that the full resolve which happened at
the end of every frame was converted to a partial resolve, allowing the
framebuffer to retain compression.

According to Caleb Callaway's testing, enabling this modifier positively
impacts the FPS of the following game benchmarks:

 - Strange Brigade.vk-g6              +12.78%
 - Strange Brigade.dx12vk-g6          + 9.33%
 - Shadow of the Tomb Raider.vk-g6-lx + 2.37%
 - Dota 2 (replay Jul 2020).vk-g6     + 2.28%

Thanks to Felix Degrood for pointing out that Strange Brigade would
benefit from this optimization.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>