Tom Rini [Sat, 29 Oct 2022 00:27:12 +0000 (20:27 -0400)]
global: Migrate CONFIG_SYS_MPC8* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 29 Oct 2022 00:27:11 +0000 (20:27 -0400)]
Convert CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:10 +0000 (20:27 -0400)]
Convert CONFIG_SYS_NONCACHED_MEMORY to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_NONCACHED_MEMORY
To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to
gate if we are going to have noncached_... functions available and then
continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said
cache. We make this new option depend on both the architectures which
implement support and the drivers which make use of it.
Cc: Tom Warren <twarren@nvidia.com>
Cc: Mingming lee <mingming.lee@mediatek.com>
Cc: "Ying-Chun Liu (PaulLiu)" <paul.liu@linaro.org>
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:09 +0000 (20:27 -0400)]
SYS_NONCACHED_MEMORY: Correct comment in common/board_f.c
The comment block in reserve_noncached has a typo in one filename and
an incorrect filename in another function reference. Correct both of
these.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:08 +0000 (20:27 -0400)]
mediatek: Include <linux/sizes.h> where needed
These files reference SZ_ macros without including <linux/sizes.h>,
correct this.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:07 +0000 (20:27 -0400)]
Convert CONFIG_SYS_MONITOR_LEN to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MONITOR_LEN
To do this, we set a default of 0 for everyone because there are a
number of cases where we define CONFIG_SYS_MONITOR_LEN but the only
impact is that we set TOTAL_MALLOC_LEN to be CONFIG_SYS_MALLOC_LEN +
CONFIG_ENV_SIZE, so we must continue to allow all boards to set this
value. Update the SPL code to use 200 KB as the default raw U-Boot size
directly, if we don't have a real CONFIG_SYS_MONITOR_LEN value.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:06 +0000 (20:27 -0400)]
Convert CONFIG_SYS_MMC_MAX_DEVICE to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MMC_MAX_DEVICE
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Sat, 29 Oct 2022 00:27:05 +0000 (20:27 -0400)]
Convert CONFIG_SYS_MMC_MAX_BLK_COUNT to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MMC_MAX_BLK_COUNT
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Tom Rini [Sat, 29 Oct 2022 00:27:04 +0000 (20:27 -0400)]
Convert CONFIG_SYS_MAX_NAND_DEVICE to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MAX_NAND_DEVICE
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:03 +0000 (20:27 -0400)]
rtc: Remove unused drivers
These drivers are not enabled anywhere, remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:02 +0000 (20:27 -0400)]
Convert CONFIG_SYS_LOADS_BAUD_CHANGE et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_LOADS_BAUD_CHANGE
CONFIG_LOADS_ECHO
As part of this, we move CMD_SAVES to be after CMD_LOADS as they are
logically related (load or save an s-record format file) and this makes
grouping of CONFIG_SYS_LOADS_BAUD_CHANGE easier.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:01 +0000 (20:27 -0400)]
powerpc: Migrate SYS_L3_SIZE to Kconfig
Introduce three options, one for each observed L3 cache size, and have
the size select'd as needed.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:27:00 +0000 (20:27 -0400)]
powerpc: Migrate SYS_L2_SIZE to Kconfig
Introduce two options, one for each observed L2 cache size, and have the
size select'd as needed.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:59 +0000 (20:26 -0400)]
fs: jffs2: Move SYS_JFFS2_SORT_FRAGMENTS to Kconfig
Move the symbol SYS_JFFS2_SORT_FRAGMENTS to Kconfig and use the only
remaining part of doc/README.JFFS2 that is still relevant and useful to
the help for this option.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:58 +0000 (20:26 -0400)]
Remove unused symbols CONFIG_SYS_JFFS2_FIRST_BANK et al
This removes the following symbols:
CONFIG_RTC_MCFRRTC
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LIME_SIZE
CONFIG_SYS_MAMR
CONFIG_SYS_MCFRRTC_BASE
CONFIG_SYS_MONITOR_SEC
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:57 +0000 (20:26 -0400)]
Convert CONFIG_SYS_INTERLAKEN et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_INTERLAKEN
CONFIG_SYS_ISA_IO
CONFIG_SYS_ISA_IO_BASE_ADDRESS
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:56 +0000 (20:26 -0400)]
Remove dead code
This header is unreferenced, remove.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:55 +0000 (20:26 -0400)]
Convert CONFIG_SYS_INIT_RAM_LOCK to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_INIT_RAM_LOCK
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 29 Oct 2022 00:26:54 +0000 (20:26 -0400)]
Convert CONFIG_SYS_I2C_INIT_BOARD to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_I2C_INIT_BOARD
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 8 Nov 2022 14:45:10 +0000 (09:45 -0500)]
Merge tag 'dm-pull-7nov22' of https://source.denx.de/u-boot/custodians/u-boot-dm
sandbox UCLASS_HOST
Michal Suchanek [Tue, 27 Sep 2022 21:23:53 +0000 (23:23 +0200)]
dm: blk: Add probe in blk_first_device/blk_next_device
The description claims that the device is probed but it isn't.
Add the device_probe() call.
Also consolidate the iteration into one function.
Fixes:
8a5cbc065d ("dm: blk: Use uclass_find_first/next_device() in blk_first/next_device()")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Simon Glass [Sun, 30 Oct 2022 01:47:19 +0000 (19:47 -0600)]
dm: Add tests for the sandbox host driver
Add some unit tests for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:18 +0000 (19:47 -0600)]
dm: Add documentation for host command and implementation
Document the 'host' command and also the internals of how it is
implemented.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:17 +0000 (19:47 -0600)]
dm: sandbox: Switch over to using the new host uclass
Update the sandbox implementation to use UCLASS_HOST and adjust all
the pieces to continue to work:
- Update the 'host' command to use the new API
- Replace various uses of UCLASS_ROOT with UCLASS_HOST
- Disable test_eficonfig since it doesn't work (this should have a unit
test to allow this to be debugged)
- Update the blk test to use the new API
- Drop the old header file
Unfortunately it does not seem to be possible to split this change up
further.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:16 +0000 (19:47 -0600)]
dm: sandbox: Create a block driver
Create a block driver for the new HOST uclass. This handles attaching and
detaching host files.
For now the uclass is not used but this will be plumbed in with future
patches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:15 +0000 (19:47 -0600)]
dm: sandbox: Create a new HOST uclass
Sandbox supports block devices which can access files on the host machine.
At present there is no uclass for this. The devices are attached to the
root devic. The block-device type is therefore set to UCLASS_ROOT which
is confusing.
Block devices should be attached to a 'media' device instead, something
which handles access to the actual media and provides the block driver
for the block device.
Create a new uclass to handle this. It supports two operations, to attach
and detach a file on the host machine.
For now this is not fully plumbed in.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:14 +0000 (19:47 -0600)]
dm: blk: Tidy up obtaining a block device from its parent
This function now finds its block-device child by looking for a child
device of the correct uclass (UCLASS_BLK). It cannot produce a device of
any other type, so drop the superfluous check.
Provide a version which does not probe the device, since that is often
needed when setting up the device's platdata.
Also fix up the function's comment.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:13 +0000 (19:47 -0600)]
test: Add a way to detect a test that breaks another
When running unit tests, some may have side effects which cause a
subsequent test to break. This can sometimes be seen when using 'ut dm'
or similar.
Add a new argument which allows a particular (failing) test to be run
immediately after a certain number of tests have run. This allows the
test causing the failure to be determined.
Update the documentation also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:12 +0000 (19:47 -0600)]
test: Allow showing basic information about tests
Add a 'ut info' command to show the number of suites and tests. This is
useful to get a feel for the scale of the tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:11 +0000 (19:47 -0600)]
test: doc: Add documentation for ut command
Before adding more options, document this command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:10 +0000 (19:47 -0600)]
test: Tidy up help for ut command
Sort this and put the command summary at the top instead of the bottom.
Adjust it so that the newlines are at the start of the strings, so that
there is not a blank line at the end.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:09 +0000 (19:47 -0600)]
test: Drop an unused parameter to ut_run_test_live_flat()
The select_name parameter is not used anymore. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:08 +0000 (19:47 -0600)]
dm: test: Clear the block cache after running a test
Some tests access data in block devices and so cause the cache to fill
up. This results in memory being allocated.
Some tests check the malloc usage at the beginning and then again at the
end, to ensure there is no memory leak caused by the test. The block cache
makes this difficult, since the any test may cause entries to be allocated
or even freed, if the cache becomes full.
It is simpler to clear the block cache after each test. This ensures that
it will not introduce noise in tests which check malloc usage.
Add the logic to clear the cache, using the existing blkcache_invalidate()
function. Drop the duplicate code at the same time.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:07 +0000 (19:47 -0600)]
dm: test: Drop the special function for running DM tests
This is not needed since the flag takes care of all differences. Make use
of the common function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:06 +0000 (19:47 -0600)]
test: Correct pylint warnings in fs_helper
Tidy this up so that pylint is happy. Use hex for the 1MB size and make
sure it is not a floating-point value.
Add a little main program to allow the code to be tried out, since at
present is only called from a long-running test.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:05 +0000 (19:47 -0600)]
test: Split out mk_fs function into a helper
This function is useful for other tests. Move it into common code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:04 +0000 (19:47 -0600)]
sandbox: Add missing comments for os_alarm()
Add the documentation to avoid a warning with 'make htmldocs'.
Fixes:
10107efedd5 ("sandbox: add SIGALRM-based watchdog device")
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 30 Oct 2022 01:47:03 +0000 (19:47 -0600)]
dm: sandbox: Drop non-BLK code from host implementation
This is not used anymore. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 7 Nov 2022 20:27:03 +0000 (15:27 -0500)]
Prepare v2023.01-rc1
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 7 Nov 2022 16:58:57 +0000 (11:58 -0500)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 7 Nov 2022 12:56:07 +0000 (07:56 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5) (Chris)
- Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb (Pali)
- armada: dts: Add clock to armada-ap80x uart1 (Hamish)
Chris Packham [Sat, 5 Nov 2022 04:24:00 +0000 (17:24 +1300)]
arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Sat, 5 Nov 2022 04:23:59 +0000 (17:23 +1300)]
arm: mvebu: Support for 98DX25xx/98DX35xx SoC
Add support for the Allecat5/Alleycat5X SoC. These are L3 switches with
an integrated CPU (referred to as the CnM block in Marvell's
documentation). These have dual ARMv8.2 CPUs (Cortex-A55). This support
has been ported from Marvell's SDK which is based on a much older
version of U-Boot.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Chris Packham [Sat, 5 Nov 2022 04:23:58 +0000 (17:23 +1300)]
pinctrl: mvebu: Add AlleyCat5 support
This uses the same IP block as the Armada-8K SoCs.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Sat, 5 Nov 2022 04:23:57 +0000 (17:23 +1300)]
usb: ehci: ehci-marvell: Support for marvell,ac5-ehci
Unlike the other 64-bit mvebu SoCs the AlleyCat5 uses the older ehci
block from the 32-bit SoCs. Adapt the ehci-marvell.c driver to cope with
the fact that the ac5 does not have the mbus infrastructure the 32-bit
SoCs have and ensure USB_EHCI_IS_TDI is selected.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Sat, 5 Nov 2022 04:23:56 +0000 (17:23 +1300)]
net: mvneta: Add support for AlleyCat5
Add support for the AlleyCat5 SoC. This lacks the mbus from the other
users of the mvneta.c driver so a new compatible string is needed to
allow for a different window configuration.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Chris Packham [Sat, 5 Nov 2022 04:23:55 +0000 (17:23 +1300)]
arm: mvebu: Don't use CONFIG_TIMER on ARM64
The 64-bit mvebu SoCs don't have a suitable timer driver so add a !ARM64
condition to the select.
Fixes:
7b530bb19e ("arm: mvebu: Use CONFIG_TIMER on all MVEBU & KIRKWOOD platforms")
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 2 Nov 2022 17:51:28 +0000 (18:51 +0100)]
Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb
File name with pattern u-boot-spl* is used on all places except in kwb
image for binary with SPL-only code. Combined binary with both SPL and
proper U-Boot in other places has file name pattern u-boot-with-spl*.
Make it consistent also for kwb image and rename u-boot-spl.kwb to
u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code.
Also update documentation about file name changes.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Hamish Martin [Thu, 20 Oct 2022 21:21:59 +0000 (10:21 +1300)]
arm: armada: dts: Add clock to armada-ap80x uart1
The uart1 node was missing the 'clock-frequency' property. This meant
the driver for this device would fail at probe.
The clock for uart1 is fed from the same source as uart0 and is a fixed
200MHz clock. This is confirmed via documentation for the CN9130 SoC
and from the equivalent code in Linux at:
<linux>/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
where uart0 and uart1 share a common 'clocks' definition.
Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Sun, 6 Nov 2022 12:51:44 +0000 (07:51 -0500)]
Merge tag 'efi-2023-01-rc1-4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-01-rc1-4
Documentation:
* Provide a document about security issue handling.
UEFI:
* Let networking support depend on NETDEVICES.
* Discover if no efi_system_partition is set.
Other:
* MAINTAINERS: add arch/arm/lib/*_efi.* to EFI_PAYLOAD.
Heinrich Schuchardt [Sun, 6 Nov 2022 00:52:13 +0000 (01:52 +0100)]
efi_loader: AllocateAddress requires page address
AllocatePages() can be called with Type=AllocateAddress. Such a call can
only succeed if *Memory points to the address of an unallocated page range.
A call with *Memory being an address that is not page aligned must not
succeed. The UEFI specification requires returning EFI_OUT_OF_RESOURCES
if the requested pages cannot be allocated.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Masahisa Kojima [Mon, 3 Oct 2022 07:12:15 +0000 (16:12 +0900)]
test/py: efi_secboot: Remove unnecessary cert-to-efi-hash-list option
'cert-to-efi-hash-list -t 0' does not work as expected, it produces
indeterminate timestamp.
$ cert-to-efi-hash-list -t 0 -s 256 db.crt dbx_hash.crl
TimeOfRevocation is 0-113-0 00:00:255
If we need the CRL revoked for all the time, just don't specify
'-t' option.
$ cert-to-efi-hash-list -s 256 db.crt dbx_hash.crl
TimeOfRevocation is 0-0-0 00:00:00
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Heinrich Schuchardt [Fri, 21 Oct 2022 06:33:44 +0000 (08:33 +0200)]
efi_loader: discover if no efi_system_partition is set
Variable efi_system_partition holds the efi_system_partition. Currently it
is initialized as:
{
.uclass_id = 0 = UCLASS_ROOT,
.denum = 0,
.part = 0,
}
This indicates that host 0:0 is the efi_system_partition and we see output
like:
=> bootefi hello
** Bad device specification host 0 **
Couldn't find partition host 0:0
To identify that no EFI system partition has been set use UCLASS_INVALID.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
AKASHI Takahiro [Fri, 21 Oct 2022 03:01:57 +0000 (12:01 +0900)]
efi_loader: remove CONFIG_EFI_SETUP_EARLY
Since the commit
a9bf024b2933 ("efi_loader: disk: a helper function to
create efi_disk objects from udevice"), CONFIG_EFI_SETUP_EARLY option is
by default on and will never be turned off.
So just remove this option.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Jan Kiszka [Fri, 14 Oct 2022 16:10:06 +0000 (18:10 +0200)]
efi_loader: Let networking support depend on NETDEVICES
CONFIG_NET does not imply that there are actually network devices
available, only CONFIG_NETDEVICES does. Changing to this dependency
obsoletes the check in Kconfig because NETDEVICES means DM_ETH.
Fixes:
0efe1bcf5c2c ("efi_loader: Add network access support")
Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Sun, 6 Nov 2022 09:23:55 +0000 (10:23 +0100)]
MAINTAINERS: add arch/arm/lib/*_efi.* to EFI_PAYLOAD
The files arch/arm/lib/*_efi.* are only relevant for the UEFI sub-system.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Thu, 3 Nov 2022 18:25:44 +0000 (14:25 -0400)]
docs: Add a basic security document
Based loosely on the Linux kernel
Documentation/admin-guide/security-bugs.rst file, create a basic
security document for U-Boot. In sum, security issues should be
disclosed in public on the mailing list if at all possible as an initial
position.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Fri, 28 Oct 2022 20:28:09 +0000 (22:28 +0200)]
doc: update sbi command example
The output of the sbi command has been changed since the last release of
the man-page. Update the example.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Fri, 4 Nov 2022 15:19:58 +0000 (11:19 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb
- 3 important fixes
Janne Grunau [Fri, 4 Nov 2022 07:38:59 +0000 (08:38 +0100)]
usb: storage: continue probe on "Invalid device"
Fixes a crash during probing of sd card readers without medium present.
Seen with the device below but reported for many other devices.
idVendor 0x0bda Realtek Semiconductor Corp.
idProduct 0x0326 Card reader
bcdDevice 11.24
iManufacturer 1 Realtek
iProduct 2 USB3.0 Card Reader
iSerial 3
201404081410
Link: https://github.com/AsahiLinux/linux/issues/44
Link: https://lists.denx.de/pipermail/u-boot/2022-July/489717.html
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Tom Rini [Fri, 4 Nov 2022 00:23:27 +0000 (20:23 -0400)]
Merge tag 'mips-pull-2022-11-03' of https://source.denx.de/u-boot/custodians/u-boot-mips
- MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
- MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO
Marek Vasut [Sun, 30 Oct 2022 22:38:35 +0000 (23:38 +0100)]
usb: Add 1ms delay after first Get Descriptor request
Logitech Unifying Receiver 046d:c52b bcdDevice 12.10 seems
sensitive about the first Get Descriptor request. If there
are any other requests in the same microframe, the device
reports bogus data, first of the descriptor parts is not
sent to the host. Wait over one microframe duration before
issuing subsequent requests to avoid probe failure with
this device, since it can be used to connect USB keyboards.
Signed-off-by: Marek Vasut <marex@denx.de>
Tested-by: Janne Grunau <j@jannau.net>
Samuel Holland [Mon, 31 Oct 2022 04:15:12 +0000 (23:15 -0500)]
usb: ohci: Use a flexible array member for portstatus
The struct is only used to overlay the MMIO region, so the behavior is
the same. This obsoletes the Kconfig option for the number of ports.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Tom Rini [Thu, 3 Nov 2022 12:29:10 +0000 (08:29 -0400)]
Merge branch '2022-11-02-assorted-updates'
- Improve arm semihosting, NPCM8xx pinctrl driver, SP804 uclass timer
driver (and enable on relevant platforms), pvblock cleanup, eeprom cmd
bugfix, add RTI watchdog nodes to k3-am64-main, evb-ast2500 config
updates.
Tom Rini [Thu, 3 Nov 2022 12:27:44 +0000 (08:27 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
Padmarao Begari [Thu, 27 Oct 2022 06:02:02 +0000 (11:32 +0530)]
riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Padmarao Begari [Thu, 27 Oct 2022 06:02:01 +0000 (11:32 +0530)]
spi: Add Microchip PolarFire SoC QSPI driver
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Padmarao Begari [Thu, 27 Oct 2022 06:02:00 +0000 (11:32 +0530)]
riscv: dts: Add QSPI NAND device node
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree.
The Winbond NAND flash memory can be connected to the
Icicle Kit by using the Mikroe Flash 5 click board and
the Pi 3 Click shield.
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Padmarao Begari [Thu, 27 Oct 2022 06:01:59 +0000 (11:31 +0530)]
riscv: dts: Update memory configuration
In the v2022.10 Icicle reference design, the seg registers have been
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Tue, 25 Oct 2022 15:03:50 +0000 (23:03 +0800)]
riscv: Rename Andes PLIC to PLICSW
As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Stefan Roese [Fri, 28 Oct 2022 12:46:29 +0000 (14:46 +0200)]
mips: mtmips: spl/Kconfig: Set CONFIG_SPL_PAD_TO to 0x0 for ARCH_MTMIPS
It was noticed that while converting CONFIG_SPL_PAD_TO to Kconfig its
value for the MIPS MT762x/8x targets got not ported correctly. Its
default is not 0x10000 instead of 0x0. This patch fixes this issue.
Fixes:
ca8a329a1b7f ("Convert CONFIG_SPL_PAD_TO et al to Kconfig")
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Ruben Winters <Ruben.Winters@gooiland-elektro.nl>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Daniel Schwierzeck [Sun, 10 Jul 2022 15:15:14 +0000 (17:15 +0200)]
MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_MIPS_TIMER_REQ
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Daniel Schwierzeck [Sun, 10 Jul 2022 15:15:13 +0000 (17:15 +0200)]
MIPS: mscc: remove unused CPU_CLOCK_RATE
CPU_CLOCK_RATE is just used once for CONFIG_SYS_MIPS_TIMER_FREQ
which is migrated to Kconfig in the next patch.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Daniel Schwierzeck [Sun, 10 Jul 2022 15:15:12 +0000 (17:15 +0200)]
MIPS: remove CONFIG_SYS_MHZ
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Daniel Schwierzeck [Sun, 10 Jul 2022 15:15:11 +0000 (17:15 +0200)]
MIPS: remove deprecated TARGET_VCT option
This board has been removed a long time ago.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Nylon Chen [Thu, 27 Oct 2022 06:25:37 +0000 (14:25 +0800)]
led: led_pwm: typo 'iverted' on code comment
change iverted to inverted.
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Cédric Le Goater [Wed, 26 Oct 2022 13:11:15 +0000 (15:11 +0200)]
configs: evb-ast2500: Set environment in SPI flash
We now have a SPI flash driver. Let's use it.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cédric Le Goater [Wed, 26 Oct 2022 13:11:14 +0000 (15:11 +0200)]
configs: evb-ast2500: Add support for FIT format
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cédric Le Goater [Wed, 26 Oct 2022 13:11:13 +0000 (15:11 +0200)]
configs: evb-ast2500: Adjust boot command
Loading a kernel image is enough.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Cédric Le Goater [Wed, 26 Oct 2022 13:11:12 +0000 (15:11 +0200)]
configs: evb-ast2500: Remove MMC support from default settings
This saves ~50K in the resulting u-boot.bin file which is important to
fit in the U-Boot partition defined in the flash layout of upstream Linux.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Christian Gmeiner [Wed, 26 Oct 2022 11:15:55 +0000 (13:15 +0200)]
arm: dts: ti: k3-am64-main: Add RTI watchdog nodes
Add the needed bus mappings for the two main RTI memory ranges and
the required device tree nodes in the main domain.
Same as kernel commit
6dd8457dc20693e2ba9054c171499b22664fd4e7
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Bin Meng [Wed, 26 Oct 2022 04:40:07 +0000 (12:40 +0800)]
treewide: Remove the unnecessary space before semicolon
%s/return ;/return;
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Baruch Siach [Sun, 23 Oct 2022 09:28:12 +0000 (12:28 +0300)]
cmd: eeprom: don't truncate target address at 32-bit
On 64-bit platforms where int is 32-bit wide, the eeprom command
parse_numeric_param() routine truncates the memory address parameter to
the lower 32-bit. Make parse_numeric_param() return long to allow
read/write of addresses beyond the lower 4GB.
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Michal Suchanek [Sat, 22 Oct 2022 14:33:05 +0000 (16:33 +0200)]
xen: pvblock: Use uclass_probe_all
Also eliminate useless code and variables.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andre Przywara [Thu, 20 Oct 2022 22:10:25 +0000 (23:10 +0100)]
highbank: switch to use the Arm SP804 DM_TIMER driver
So far the Calxeda machines were using the CONFIG_SYS_TIMER_* macros to
simply hardcode the address of the counter register of the SP804 timer.
This method is deprecated and scheduled for removal.
Use the newly introduced SP804 DM_TIMER driver to provide timer
functionality on Highbank and Midway machines. The base address and base
frequency are taken from the devicetree.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 20 Oct 2022 22:10:24 +0000 (23:10 +0100)]
highbank: scan into hb_sregs DT subnodes
The DT used for Calxeda Highbank and Midway systems exposes a "system
registers" block, modeled as a DT subnode.
This includes several clocks, including the two fixed clocks for the
main oscillator and timer.
So far U-Boot was ignorant of this special construct (a "clocks" node
within the "hb-sregs" node), as it didn't need the PLL clocks in there.
But that also meant we lost the fixed clocks, which form the base for
the UART baudrate generator and also the SP804 timer.
To allow the generic PL011 and SP804 driver to read the clock rate,
add a simple bus driver, which triggers the DT node discovery inside this
special node. As we only care about the fixed clocks (we don't have
drivers for the PLLs anyway), just ignore the address translation (for
now).
The binding is described in bindings/arm/calxeda/hb-sregs.yaml, the DT
snippet in question looks like:
=======================
sregs@
fff3c000 {
compatible = "calxeda,hb-sregs";
reg = <0xfff3c000 0x1000>;
clocks {
#address-cells = <1>;
#size-cells = <0>;
osc: oscillator {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <
33333000>;
};
....
};
};
=======================
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 20 Oct 2022 22:10:23 +0000 (23:10 +0100)]
timer: add SP804 UCLASS timer driver
The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down
timer IP with interrupt functionality, and is used in some SoCs from
various vendors.
Add a simple DM compliant timer driver, to allow users of the SP804 to
switch to DM_TIMER.
This relies on the input clock to be accessible via the DM clock
framework, which should be fine as we probably look at fixed-clock's
here anyway.
We re-program the control register in the probe() function, but keep
the divider in place, in case this has been set to something on purpose
before.
The TRM for the timer IP can be found here:
https://developer.arm.com/documentation/ddi0271/latest
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Jim Liu [Tue, 11 Oct 2022 08:09:13 +0000 (16:09 +0800)]
pinctrl: nuvoton: Add NPCM8xx pinctrl driver
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Signed-off-by: Stanley Chu <yschu@nuvoton.com>
Andre Przywara [Wed, 5 Oct 2022 16:38:49 +0000 (17:38 +0100)]
arm: smh: Allow semihosting trap calls to be inlined
Currently our semihosting trap function is somewhat fragile: we rely
on the current compiler behaviour to assign the second inline assembly
argument to the next free register (r1/x1), which happens to be the
"addr" argument to the smh_trap() function (per the calling convention).
I guess this is also the reason for the noinline attribute.
Make it explicit what we want: the "addr" argument needs to go into r1,
so we add another register variable. This allows to drop the "noinline"
attribute, so now the compiler beautifully inlines just the trap
instruction directly into the calling function.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 Oct 2022 16:38:48 +0000 (17:38 +0100)]
arm: smh: Make semihosting trap calls more robust
Commit
f4b540e25c5c("arm: smh: Fix uninitialized parameters with newer
GCCs") added a memory clobber to the semihosting inline assembly trap
calls, to avoid too eager GCC optimisation: when passing a pointer, newer
compilers couldn't be bothered to actually fill in the structure that it
pointed to, as this data would seemingly never be used (at least from the
compiler's point of view).
But instead of the memory clobber we need to tell the compiler that we are
passing an *array* instead of some generic pointer, this forces the
compiler to actually populate the data structure.
This involves some rather hideous cast, which is best hidden in a macro.
But regardless of that, we actually need the memory clobber, but for two
different reasons: explain them in comments.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 5 Oct 2022 16:38:47 +0000 (17:38 +0100)]
arm: smh: specify Thumb trap instruction
The ARM semihosting interface uses different trap instructions for
different architectures and instruction sets. So far we were using
AArch64 and ARMv7-M, and had an untested v7-A entry. The latter does
not work when building for Thumb, as can be verified by using
qemu_arm_defconfig, then enabling SEMIHOSTING and SYS_THUMB_BUILD:
==========
{standard input}:35: Error: invalid swi expression
{standard input}:35: Error: value of 1193046 too large for field of 2 bytes at 0
==========
Fix this by providing the recommended instruction[1] for Thumb, and
using the ARM instruction only when not building for Thumb. This also
removes some comment, as QEMU for ARM allows to now test this case.
Also use the opportunity to clean up the inline assembly, and just define
the actual trap instruction inside #ifdef's, to improve readability.
[1] https://developer.arm.com/documentation/dui0471/g/Semihosting/The-semihosting-interface?lang=en
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tom Rini [Wed, 2 Nov 2022 13:10:30 +0000 (09:10 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-watchdog
- cyclic: get rid of (the need for) cyclic_init() (Rasmus)
Tom Rini [Wed, 2 Nov 2022 13:09:57 +0000 (09:09 -0400)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-spi.git
- NPCM PSPI controller (Jim)
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:54 +0000 (13:50 +0200)]
cyclic: get rid of cyclic_init()
Currently, we must call cyclic_init() at some point before
cyclic_register() becomes possible. That turns out to be somewhat
awkward, especially with SPL, and has resulted in a watchdog callback
not being registered, thus causing the board to prematurely reset.
We already rely on gd->cyclic reliably being set to NULL by the asm
code that clears all of gd. Now that the cyclic list is a hlist, and
thus an empty list is represented by a NULL head pointer, and struct
cyclic_drv has no other members, we can just as well drop a level of
indirection and put the hlist_head directly in struct
global_data. This doesn't increase the size of struct global_data,
gets rid of an early malloc(), and generates slightly smaller code.
But primarily, this avoids having to call cyclic_init() early; the cyclic
infrastructure is simply ready to register callbacks as soon as we
enter C code.
We can still end up with schedule() being called from asm very early,
so we still need to check that gd itself has been properly initialized
[*], but once it has, gd->cyclic_list is perfectly fine to access, and
will just be an empty list.
As for cyclic_uninit(), it was never really the opposite of
cyclic_init() since it didn't free the struct cyclic_drv nor set
gd->cyclic to NULL. Rename it to cyclic_unregister_all() and use that
in test/, and also insert a call at the end of the board_init_f
sequence so that gd->cyclic_list is a fresh empty list before we enter
board_init_r().
A small piece of ugliness is that I had to add a cast in
cyclic_get_list() to silence a "discards 'volatile' qualifier"
warning, but that is completely equivalent to the existing handling of
the uclass_root_s list_head member.
[*] I'm not really sure where we guarantee that the register used for
gd contains 0 until it gets explicitly initialized, but that must be
the case, otherwise testing gd for being NULL would not make much sense.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:53 +0000 (13:50 +0200)]
cyclic: switch to using hlist instead of list
A hlist is headed by just a single pointer, so can only be traversed
forwards, and insertions can only happen at the head (or before/after
an existing list member). But each list node still consists of two
pointers, so arbitrary elements can still be removed in O(1).
This is precisely what we need for the cyclic_list - we never need to
traverse it backwards, and the order the callbacks appear in the list
should really not matter.
One advantage, and the main reason for doing this switch, is that an
empty list is represented by a NULL head pointer, so unlike a
list_head, it does not need separate C code to initialize - a
memset(,0,) of the containing structure is sufficient.
This is mostly mechanical:
- The iterators are updated with an h prefix, and the type of the
temporary variable changed to struct hlist_node*.
- Adding/removing is now just hlist_add_head (and not tail) and
hlist_del().
- struct members and function return values updated.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:52 +0000 (13:50 +0200)]
list.h: synchronize hlist_for_each_entry* iterators with linux
All the way back in 2013, the linux kernel updated the four
hlist_for_each_entry* iterators to require one less auxiliary
variable:
commit
b67bfe0d42cac56c512dd5da4b1b347a23f4b70a
Author: Sasha Levin <sasha.levin@oracle.com>
Date: Wed Feb 27 17:06:00 2013 -0800
hlist: drop the node parameter from iterators
Currently, there is only one "user" of any of these, namely in
fs/ubifs/super.c, but that actually uses the "new-style" form, and
is (obviously, or it wouldn't have built) inside #ifndef __UBOOT__.
Before adding actual users of these, import the version as of linux
v6.1-rc1, including the hlist_entry_safe() helper used by the new
versions.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:51 +0000 (13:50 +0200)]
cyclic: drop redundant cyclic_ready flag
We're already relying on gd->cyclic being NULL before cyclic_init() is
called - i.e., we're relying on all of gd being zeroed before entering
any C code. And when we do populate gd->cyclic, its ->cyclic_ready
member is automatically set to true. So we can actually just rely on
testing gd->cyclic itself.
The only wrinkle is that cyclic_uninit() actually did set
->cyclic_ready to false. However, since it doesn't free gd->cyclic,
the cyclic infrastructure is actually still ready (i.e., the list_head
is properly initialized as an empty list).
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Rasmus Villemoes [Fri, 28 Oct 2022 11:50:50 +0000 (13:50 +0200)]
cyclic: use a flag in gd->flags for recursion protection
As a preparation for future patches, use a flag in gd->flags rather
than a separate member in (the singleton) struct cyclic_drv to keep
track of whether we're already inside cyclic_run().
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com> # imx8mm-venice-*
Tom Rini [Tue, 1 Nov 2022 13:32:21 +0000 (09:32 -0400)]
Merge branch '2022-10-31-FWU-add-FWU-multi-bank-update-feature-support'
To quote the author:
The patchset adds support for the FWU Multi Bank Update[1]
feature. Certain aspects of the Dependable Boot[2] specification have
also been implemented.
The FWU multi bank update feature is used for supporting multiple
sets(also called banks) of firmware image(s), allowing the platform to
boot from a different bank, in case it fails to boot from the active
bank. This functionality is supported by keeping the relevant
information in a structure called metadata, which provides information
on the images. Among other parameters, the metadata structure contains
information on the currect active bank that is being used to boot
image(s).
Functionality is being added to work with the UEFI capsule driver in
u-boot. The metadata is read to gather information on the update bank,
which is the bank to which the firmware images would be flashed to. On
a successful completion of the update of all components, the active
bank field in the metadata is updated, to reflect the bank from which
the platform will boot on the subsequent boots.
Currently, the feature is being enabled on the STM32MP157C-DK2 and
Synquacer boards. The DK2 board boots a FIP image from a uSD card
partitioned with the GPT partioning scheme, while the Synquacer board
boots a FIP image from a MTD partitioned SPI NOR flash device.
This feature also requires changes in a previous stage of
bootloader, which parses the metadata and selects the bank to boot the
image(s) from. Support has being added in tf-a(BL2 stage) for the
STM32MP157C-DK2 board to boot the active bank images. These changes
have been merged to the upstream tf-a repository.
The patch for adding a python test for the feature has been developed,
and was sent in the version 5 of the patches[3]. However, the test
script depends on adding support for the feature on MTD SPI NOR
devices, and that is being done as part of the Synquacer
patches. Hence these set of patches do not have the test script for
the feature. That will be added through the patches for adding support
for the feauture on Synquacer platform.
[1] - https://developer.arm.com/documentation/den0118/a
[2] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/
6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf
[3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html
Sughosh Ganu [Fri, 21 Oct 2022 12:46:08 +0000 (18:16 +0530)]
FWU: doc: Add documentation for the FWU feature
Add documentation for the FWU Multi Bank Update feature. The document
describes the steps needed for setting up the platform for the
feature, as well as steps for enabling the feature on the platform.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>