Bin Meng [Fri, 10 Aug 2018 09:39:36 +0000 (02:39 -0700)]
x86: tsc: Try hardware calibration first
At present if TSC frequency is provided in the device tree, it takes
precedence over hardware calibration result. This swaps the order to
try hardware calibration first and uses device tree as last resort.
This can be helpful when a generic dts (eg: coreboot/efi payload) is
supposed to work on as many hardware as possible, including emulators
like QEMU where TSC hardware calibration sometimes fails.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Bin Meng [Fri, 10 Aug 2018 09:39:35 +0000 (02:39 -0700)]
x86: dts: Remove coreboot_fb.dtsi
There is no need to keep a separate coreboot_fb.dtsi since now we
have a generic coreboot payload dts.
While we are here, this also remove the out-of-date description in
the documentation regarding to coreboot framebuffer driver with
U-Boot loaded as a payload from coreboot. As the testing result with
QEMU 2.5.0 shows, the driver just works like a charm.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Fri, 10 Aug 2018 09:39:34 +0000 (02:39 -0700)]
x86: Remove support for Advantech SOM-6896
Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Bin Meng [Fri, 10 Aug 2018 09:39:33 +0000 (02:39 -0700)]
x86: coreboot: Add generic coreboot payload support
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.
But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Andy Shevchenko [Mon, 6 Aug 2018 16:00:22 +0000 (19:00 +0300)]
Makefile: Don't generate position independent code
Since gcc-8 the --enable-default-pie starts producing code which assembler
can't translate in case of U-Boot. The build fails with
{standard input}: Assembler messages:
{standard input}:21100: Error: junk at end of line, first unrecognized character is `@'
{standard input}:21120: Error: junk at end of line, first unrecognized character is `@'
and so on.
This is usually the case for x86 platform because in many cases it uses host
compiler from the Linux distributions, where PIE is enabled by default.
Previously (gcc-7 and earlier) that was a potential issue due to absence of
constructions like
.long end.5561@gotoff-start.5558@gotoff
which are a cause of above error messages in gcc-8.
Fix all these by disabling PIE on Makefile level.
Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Peng Fan [Thu, 26 Jul 2018 11:47:24 +0000 (19:47 +0800)]
drivers: regulator: fixed: add u-boot, off-on-delay-us
Add u-boot,off-on-delay-us for fixed regulator.
Depends on board design, the gpio regulator sometimes
connects with a big capacitance. When need to off, then
on the regulator, if there is no enough delay,
the voltage does not drop to 0, so introduce this
property to handle such case.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Michal Simek [Thu, 19 Jul 2018 06:45:45 +0000 (08:45 +0200)]
env: Merge Rockchip, Sunxi, Zynq and ZynqMP
There is no reason to have the same Kconfig options for different SoCs
separately. The patch is merging them together.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
[trini: Fix ENV_SIZE around ENV_IS_NOWHERE]
Signed-off-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Adam Ford [Fri, 10 Aug 2018 10:05:22 +0000 (05:05 -0500)]
Convert CONFIG_SYS_I2C_DAVINCI to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_I2C_DAVINCI
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Tue, 7 Aug 2018 12:08:32 +0000 (07:08 -0500)]
Removed unused references to CONFIG_SERIALx
After creating CONS_INDEX and migrating a bunch of boards to it,
there are a bunch of defined references to CONFIG_SERIALx which
are not referenced in any C code or #ifdef, so they can now be
removed
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Mon, 6 Aug 2018 19:26:50 +0000 (14:26 -0500)]
Convert CONFIG_TWL4030_LED et al to Kconfig
This converts the following to Kconfig:
CONFIG_TWL4030_LED
CONFIG_TWL4030_INPUT
This also removes dead references to:
CONFIG_TWL4030_KEYPAD
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Thu, 2 Aug 2018 13:50:20 +0000 (08:50 -0500)]
Convert CONFIG_VIDEO_OMAP3 to Kconfig
This converts the following to Kconfig:
CONFIG_VIDEO_OMAP3
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Sun, 29 Jul 2018 18:13:29 +0000 (13:13 -0500)]
Convert CONFIG_MISC_INIT_R to Kconfig
This converts the following to Kconfig:
CONFIG_MISC_INIT_R
Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Update the defaults logic slightly]
Signed-off-by: Tom Rini <trini@konsulko.com>
Alex Kiernan [Sat, 21 Jul 2018 20:25:33 +0000 (20:25 +0000)]
Migrate bootlimit to Kconfig
Migrate boards which set bootlimit in the environment to Kconfig.
We exclude gurnard_defconfig which includes a bootlimit=, but doesn't set
CONFIG_BOOTCOUNT_LIMIT, so we'd fail to include a bootlimit setting
if we migrated it.
display5_defconfig and display5_factory_defconfig share a SYS_CONFIG_NAME,
but only display5_defconfig enables CONFIG_BOOTCOUNT_LIMIT, so we fail to
set bootlimit= in display5_factory_defconfig. This is okay because the
display5_factory_defconfig doesn't need to have it set, as it is only
meant to prepare the board in the factory.
Environment changes for all modified configs as seen from buildman:
boards.cfg is up to date. Nothing to do.
Summary of 3 commits for 32 boards (8 threads, 1 job per thread)
01: Merge git://git.denx.de/u-boot-x86
arm: + draco etamin rastaban pxm2 display5 thuban rut
02: Add BOOTCOUNT_BOOTLIMIT to set reboot limit
03: Migrate bootlimit to Kconfig
- display5_factory: bootlimit=3
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Alex Kiernan [Sat, 21 Jul 2018 20:25:32 +0000 (20:25 +0000)]
Add BOOTCOUNT_BOOTLIMIT to set reboot limit
Add ability to set environment bootlimit from Kconfig
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Adam Ford [Sat, 21 Jul 2018 04:03:57 +0000 (23:03 -0500)]
Convert CONFIG_MII et al to Kconfig
This converts the following to Kconfig:
CONFIG_MII
CONFIG_DRIVER_TI_EMAC
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Fri, 17 Aug 2018 08:16:36 +0000 (10:16 +0200)]
dts: Fix typo in OF_LIVE Kconfig help
Fix typo in Kconfig description.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Goldschmidt [Thu, 16 Aug 2018 07:44:55 +0000 (09:44 +0200)]
kconfig: fix typo 'parition'
Replaced misspelled words "parition"/"paritioning" (missing 't') in two
Kconfig files by correct words "partition"/"partitioning"
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tom Rini [Fri, 17 Aug 2018 11:25:04 +0000 (07:25 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
Tom Rini [Fri, 17 Aug 2018 11:24:34 +0000 (07:24 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Thu, 16 Aug 2018 12:16:24 +0000 (08:16 -0400)]
configs: Migrate CONFIG_NR_DRAM_BANKS
We have the following cases:
- CONFIG_NR_DRAM_BANKS was defined, migrate normally
- CONFIG_NR_DRAM_BANKS_MAX was defined and then used for
CONFIG_NR_DRAM_BANKS after a check, just migrate it over now.
- CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 +
2), set this to 8.
Signed-off-by: Tom Rini <trini@konsulko.com>
Ramon Fried [Mon, 13 Aug 2018 22:00:04 +0000 (01:00 +0300)]
Kconfig: Migrate CONFIG_NR_DRAM_BANKS
Move CONFIG_NR_DRAM_BANKS from headers to Kconfig.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Ramon Fried [Mon, 13 Aug 2018 21:35:42 +0000 (00:35 +0300)]
fdt_support: Use CONFIG_NR_DRAM_BANKS if necessary
If CONFIG_NR_DRAM_BANKS is bigger than the default
value (4) define MEMORY_BANKS_MAX as CONFIG_NR_DRAM_BANKS.
Fixes:
2a1f4f1758b5 ("Revert "fdt_support: Use CONFIG_NR_DRAM_BANKS if defined"")
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Tom Rini [Thu, 16 Aug 2018 20:44:19 +0000 (16:44 -0400)]
CONFIG_SYS_GENERIC_BOARD: Finish migration
While we have long since migrated to CONFIG_SYS_GENERIC_BOARD being
enabled, we had just a few places left that still referenced or defined
it. Update.
Signed-off-by: Tom Rini <trini@konsulko.com>
Ley Foon Tan [Wed, 15 Aug 2018 18:20:17 +0000 (02:20 +0800)]
arm: socfpga: Fix SYSMGR_FPGAINTF_EMACx bit mask
Bitmask for EMAC should be bit-0, EMAC1 bit-8 and EMAC2 bit-16.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Wed, 8 Aug 2018 13:06:03 +0000 (15:06 +0200)]
ARM: rmobile: Enable USB PHY on Gen2
Enable support for USB PHY on the R-Car Gen2. This allows for both
of the USB host ports to be used on such boards.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sun, 5 Aug 2018 13:22:19 +0000 (15:22 +0200)]
phy: rcar: Add R-Car Gen2 PHY driver
Add a PHY driver for the R-Car Gen2 which allows configuring the mux
connected to the EHCI controllers and USBHS controller.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 7 Aug 2018 10:24:35 +0000 (12:24 +0200)]
phy: Fix off-by-one error when parsing DT PHY bindings
The code fails to copy the last PHY phandle argument, so it is
missing from the adjusted phandle args and the consumer cannot
use it to determine what the PHY should do.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Tom Rini [Tue, 14 Aug 2018 01:20:57 +0000 (21:20 -0400)]
Prepare v2018.09-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 14 Aug 2018 00:05:58 +0000 (20:05 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Marek Vasut [Mon, 6 Aug 2018 19:42:05 +0000 (21:42 +0200)]
ARM: socfpga: clk: Convert to clock framework
Use clock framework functions to fetch clock information now that there
is a clock driver for Arria10, instead of custom coded register parsing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Wed, 1 Aug 2018 16:28:35 +0000 (18:28 +0200)]
mmc: socfpga: Add clock framework support
Add support for fetching the clock frequency both using the legacy
method in case clock framework is disabled as well as via the clock
framework if it is enabled. This allows for migration to the clock
framework on platforms which supports it while not breaking legacy
platforms. That said, the legacy method must be removed eventually.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Tue, 31 Jul 2018 15:58:07 +0000 (17:58 +0200)]
clk: socfpga: Add initial Arria10 clock driver
Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.
Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 6 Aug 2018 20:07:40 +0000 (22:07 +0200)]
ARM: dts: socfpga: Add u-boot,dm-pre-reloc to necessary clock nodes
Add the pre-reloc DT markers to clock nodes needed in SPL and early
U-Boot stages. This is required to let the Arria10 clock driver start
early and provide clock information for UART and SDMMC.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Tue, 31 Jul 2018 15:33:42 +0000 (17:33 +0200)]
ARM: socfpga: clk: Drop unused variables on Arria10
The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 6 Aug 2018 19:47:50 +0000 (21:47 +0200)]
ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 30 Jul 2018 13:56:19 +0000 (15:56 +0200)]
ARM: socfpga: clk: Obtain handoff base clock via DM
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 19:02:54 +0000 (21:02 +0200)]
ARM: socfpga: Enable DM ethernet on A10
Enable DM ethernet framework on Arria10, so that the designware GMAC
can be probed from DT as it should be.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 18:06:46 +0000 (20:06 +0200)]
ARM: socfpga: Remove adhoc ethernet reset and configuration
Remove ad-hoc ethernet syscon registers configuration and reset support.
Reset is now handled by the reset framework and the syscon registers are
set in the dwmac_socfpga.c driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 16:57:08 +0000 (18:57 +0200)]
ARM: socfpga: Zap unused reset code
Remove code from the reset manager that is never called.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 17:32:14 +0000 (19:32 +0200)]
net: designware: socfpga: Add Arria10 extras
Add wrapper around the designware MAC driver to handle the SoCFPGA
specific configuration bits. On Arria10, this is configuration of
syscon phy_intf.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Sun, 15 Apr 2018 14:29:12 +0000 (16:29 +0200)]
ARM: socfpga: Zap all the UART handling complexity
The UART reset handling is now done via reset framework using the
SoCFPGA reset driver. The UART console assignment is done using the
DM and console framework. Nuke all this comlexity, since it is just
duplicating the same functionality, badly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Marek Vasut [Mon, 13 Aug 2018 16:32:38 +0000 (18:32 +0200)]
ARM: socfpga: Enable DM I2C framework on A10
Enable the DM I2C framework on Arria10, so that the DM capable
Designware I2C driver can handle the reset via DM reset framework.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 16:32:38 +0000 (18:32 +0200)]
ARM: socfpga: Enable DM reset framework on A10
Enable the DM reset framework and DM reset driver on Arria10 both
in U-Boot and in SPL. This lets U-Boot parse reset control from DT.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 18:40:54 +0000 (20:40 +0200)]
ARM: dts: socfpga: Add i2c alias to A10 SoCDK
The A10 SoCDK is missing the I2C bus alias, so DM I2C cannot assign
the I2C bus a bus number. Add the missing alias.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 18:40:44 +0000 (20:40 +0200)]
ARM: dts: socfpga: Add missing I2C resets
The I2Cx resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 18:24:20 +0000 (20:24 +0200)]
ARM: dts: socfpga: Fix Arria10 GMAC resets
Add the GMAC0,1 OCP resets, which must also be ungated for those GMACs
to work and add GMAC2 reset and OCP resets which were missing altogether.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 16:42:39 +0000 (18:42 +0200)]
ARM: dts: socfpga: Add missing UART resets
The UART0 and UART1 resets are missing from DT, so the reset manager
cannot control them. Add the missing DT reset entries.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 13 Aug 2018 16:42:32 +0000 (18:42 +0200)]
ARM: dts: socfpga: Flag reset manager on A10 as pre-reloc
The Altera reset manager block must be available very early on, since
it controls ie. UART resets. Flag it as pre-reloc.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Marek Vasut [Mon, 30 Jul 2018 11:58:54 +0000 (13:58 +0200)]
ARM: socfpga: Register the FPGA on A10 in SPL again
The restructuring of the SPL dropped registration of the FPGA in SPL,
readd it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Fixes:
c859f2a77d98 ("arm: socfpga: Restructure the SPL file")
Simon Goldschmidt [Mon, 13 Aug 2018 19:34:35 +0000 (21:34 +0200)]
arm: socfpga: gen5: combine some init code for SPL and U-Boot
Some of the code for low level system initialization in SPL's
board_init_f() and U-Boot's arch_early_init_r() is the same,
so let's combine it into a single function called from both.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Simon Goldschmidt [Mon, 13 Aug 2018 19:34:33 +0000 (21:34 +0200)]
arm: socfpga: fix device trees to work with DM serial
Device trees need to have the serial console device available
before relocation and require a stdout-path in chosen at least
for SPL to have a console.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Patrice Chotard [Mon, 6 Aug 2018 09:52:23 +0000 (11:52 +0200)]
MAINTAINERS: Update STM32MP fragments
Add new drivers
Add Christophe Kerello and myself as maintainers
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrick Delaunay [Mon, 6 Aug 2018 09:25:42 +0000 (11:25 +0200)]
ARM: dts: stm32f4: Fix DT dtc warnings
This patch fix the following warnings for for stm32f429
evaluation and discovery boards:
unnecessary #address-cells/#size-cells without "ranges" or
child "reg" property
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Mon, 6 Aug 2018 07:54:04 +0000 (09:54 +0200)]
ARM: dts: stm32mp157: Add ADC DT node
Add ADC device tree node. This allows to get analog conversions on
stm32mp157.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Mon, 6 Aug 2018 07:38:18 +0000 (09:38 +0200)]
ARM: dts: stm32: remove cd-inverted for stm32f746-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.
Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Mon, 6 Aug 2018 07:38:17 +0000 (09:38 +0200)]
ARM: dts: stm32: remove cd-inverted for stm32f769-disco
As cd-inverted property is no more used by arm_pl180_mmci driver,
remove it. Update cd-gpios active level accordingly.
Reported-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Derald D. Woods [Mon, 6 Aug 2018 04:51:31 +0000 (23:51 -0500)]
ARM: omap3: evm: Enable CONFIG_BLK and misc. cleanup
This commit enables CONFIG_BLK and removes USB_STORAGE which is awaiting
proper implementation for current U-Boot interfaces. Additionally the
console selection is now handled by Kconfig and no longer needs to be in
the config header. CONFIG_SYS_MALLOC_F_LEN=0x2000 was added to sync with
other boards. CONFIG_SPL_BLK and CONFIG_SPL_DM_MMC are disabled because
they currently do not allow the OMAP3-EVM (OMAP34XX) to actually boot.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Miquel Raynal [Sun, 5 Aug 2018 16:53:07 +0000 (18:53 +0200)]
tpm: sandbox: fix wrong assignment with a simplification
The recv variable in sandbox_tpm2_fill_buf() is a pointer on a pointer
of a char array. It means accessing *recv is the char array pointer
itself while **recv is the first character of that array. There is no
need for such indirection here, so simplify the code.
Simplifying things will make the last assignment right: "*recv = NULL"
is now correct. The issue has been found by the following Coverity
Scan report:
CID 183371: Incorrect expression (UNUSED_VALUE)
Assigning value "4UL" to "*recv" here, but that stored value is overwritten before it can be used.
232 *recv += sizeof(rc);
233
234 /* Add trailing \0 */
235 *recv = NULL;
While at simplifying things, use '\0' instead of NULL when adding an
empty char at the end of the buffer.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Miquel Raynal [Sun, 5 Aug 2018 16:53:06 +0000 (18:53 +0200)]
tpm: sandbox: fix wrong check on pcr_map
The second check on pcr_map in sandbox_tpm2_xfer() is wrong. It should
check for pcr_map not being empty. Instead, it is a pure copy/paste of
the first check which is redundant.
This has been found thanks to a Coverity Scan report:
CID 183370: Memory - illegal accesses (UNINIT)
Using uninitialized value "pcr_index".
put_unaligned_be32(tpm->pcr_extensions[pcr_index], recv);
This is because pcr_index is initialized only if the user input is
correct, ie. at least one valid bit is set in pcr_map.
Fix the second check and also initialize pcr_index to 0 (which is
harmless in case of error) to make Coverity Scan happy.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Ramon Fried [Fri, 3 Aug 2018 17:56:27 +0000 (20:56 +0300)]
MAINTAINERS: Add more sources to Arch Snapdragon
Add scattered driver files around the source tree
that belongs to Snapdragon arch. Not sure why they
were not included in the first place.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Ramon Fried [Fri, 3 Aug 2018 13:31:02 +0000 (16:31 +0300)]
db410c: add FIT support
1. Add FIT support for DB410c defconfig.
2. Don't overwrite bootargs (they're already
defined in Linux device tree for DB410c.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Ramon Fried [Fri, 3 Aug 2018 13:25:37 +0000 (16:25 +0300)]
db410: alter WLAN/BT MAC address fixup
Change the way MAC address fixup is done:
1. Stop using LK handed device-tree and calculate
the MAC address our own.
2. Allow overriding the generated MACS with environment variables:
"wlanaddr" and "btaddr".
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Ramon Fried [Fri, 3 Aug 2018 13:25:36 +0000 (16:25 +0300)]
snapdragon: added MAC generation functions
Add support for generation of unique MAC address
that is derived from board serial.
Algorithm for generation of MAC taken from LK.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Ramon Fried [Fri, 3 Aug 2018 13:25:35 +0000 (16:25 +0300)]
snapdragon: added msm_board_serial() func
This commit adds a function to get the board
serial number.
In snapdragon it's actually the eMMC serial number.
Function added in a new file misc.c that will
include further snapdragon miscellaneous functions.
Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
Patrice Chotard [Fri, 3 Aug 2018 11:09:55 +0000 (13:09 +0200)]
stm32f7: board: Fix memory init
Commit
1473b12ad0b3 ("lib: fdtdec: Update ram_base to store ram start
adddress") brings regression on STM32F7 which can't boot.
Use fdtdec_setup_mem_size_base() to setup memory base and size.
Use fdtdec_setup_memory_banksize() to setup memory bank base and size.
Reported-by: Mark Olsson <mark@markolsson.se>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Mark Olsson <mark@markolsson.se>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:21 +0000 (11:46 +0200)]
configs: stm32f429-evaluation: Add DISTRO_DEFAULT support
Add DISTRO_DEFAULT support to be able to boot on mmc
by default on boot.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:20 +0000 (11:46 +0200)]
configs: stm32f469-discovery: Add DISTRO_DEFAULT support
Add DISTRO_DEFAULT support to be able to boot on mmc
by default on boot.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:19 +0000 (11:46 +0200)]
configs: stm32h743-discovery: Add DISTRO_DEFAULT support
Add DISTRO_DEFAULT support to be able to boot on
mmc by default on boot.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:18 +0000 (11:46 +0200)]
configs: stm32h743-evaluation: Add DISTRO_DEFAULT support
Add DISTRO_DEFAULT support to be able to boot on mmc
by default on boot.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:17 +0000 (11:46 +0200)]
configs: stm32f4xx: Remove CONFIG_SYS_RAM_FREQ_DIV
Since commit
bfea69ad2793 ("stm32f7: sdram: correct sdram
configuration as per micron sdram"), CONFIG_SYS_RAM_FREQ_DIV
flag is no more used, remove it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:16 +0000 (11:46 +0200)]
configs: stm32h7xx: Migrate CONFIG_CMD_CACHE to defconfig
Remove CONFIG_CMD_CACHE from include/configs/stm32h7xx.h
and enable it in stm32h7xx_defconfig
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:15 +0000 (11:46 +0200)]
configs: stm32f746-disco: Migrate CONFIG_CMD_CACHE to defconfig
Remove CONFIG_CMD_CACHE from include/configs/stm32f746-disco.h
and enable it in stm32f746-disco_defconfig
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:14 +0000 (11:46 +0200)]
configs: stm32f4xx: Enable ICACHE and DCACHE
Enable instruction and data caches.
Fix boot_sd command as since commit
d409c962169b ("armv7m: disable
icache before linux booting"), instruction cache is automatically
disable before linux booting. "icache off" from boot_sd command
becomes useless, remove it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:13 +0000 (11:46 +0200)]
configs: stm32f429-disco: Remove CONFIG_SYS_RAM_CS
This flag is not used, remove it.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:12 +0000 (11:46 +0200)]
configs: stm32fxxx: Remove CONFIG_SYS_CLK_FREQ
Since commit
aa5e3e22f4d6 ("board: stm32: switch to DM STM32 timer")
SYS_CLK_FREQ is useless, remove it from stm32f4 and stm32f7 boards.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Patrice Chotard [Fri, 3 Aug 2018 09:46:11 +0000 (11:46 +0200)]
board: stm32: use bi_dram[0].start instead of hardcoded value
Use gd->bd->bi_dram[0].start initialized from DT instead of using
hardcoded CONFIG_SYS_SDRAM_BASE from config file.
Remove unused CONFIG_SYS_RAM_BASE and CONFIG_SYS_SDRAM_BASE defines.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Eugen Hristev [Fri, 3 Aug 2018 09:10:49 +0000 (12:10 +0300)]
clk: at91: utmi: add timeout for utmi lock
In case the slow clock is not properly configured, the UTMI clock
cannot lock the PLL, because UPLLCOUNT will "wait X slow clock cycles".
In this case U-boot will loop indefinitely.
Added a timeout in this case, to start U-boot even if UTMI clock is
not enabled, so the user can use different media if needed, or investigate.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Thomas Fitzsimmons [Fri, 27 Jul 2018 03:02:47 +0000 (23:02 -0400)]
arm: bcm7445: Move config defines to bcm7445.h
Move some configuration #defines that do not apply to other bcmstb
boards from bcmstb.h to bcm7445.h.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Thomas Fitzsimmons [Fri, 27 Jul 2018 02:55:37 +0000 (22:55 -0400)]
arm: bcm7445: Fix parallel make race condition
Move the contents of prior_stage.h into bcmstb.h to prevent a build
failure when bcmstb.h is #include'ed before the asm/arch symbolic link
is present.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Caliph Nomble [Thu, 26 Jul 2018 02:13:03 +0000 (22:13 -0400)]
rsa: Fix LibreSSL before v2.7.0
Fix LibreSSL compilation for versions before v2.7.0.
Signed-off-by: Caliph Nomble <nomble@palism.com>
Reviewed-by: Jonathan Gray <jsg@jsg.id.au>
Heinrich Schuchardt [Sat, 11 Aug 2018 13:52:14 +0000 (15:52 +0200)]
fs: fix typo 'dumm'
%s/dumm /dummy /
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Igor Opaniuk [Fri, 10 Aug 2018 13:59:59 +0000 (16:59 +0300)]
avb2.0: add get_size_of_partition()
Implement get_size_of_partition() operation,
which is required by the latest upstream libavb [1].
[1] https://android.googlesource.com/platform/external/avb/+/android-p-preview-5
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Acked-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Tom Rini [Mon, 13 Aug 2018 16:34:55 +0000 (12:34 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Simon Goldschmidt [Mon, 13 Aug 2018 07:33:47 +0000 (09:33 +0200)]
arm: socfpga: cyclone5: handle debug uart
If CONFIG_DEBUG_UART is enabled, correctly initialize
the debug uart before console is initialized to debug
early boot problems in SPL.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Simon Goldschmidt [Mon, 13 Aug 2018 07:33:46 +0000 (09:33 +0200)]
arm: socfpga: spl_gen5: clean up malloc_base assignment
In spl_gen5's board_init_f(), gd->malloc_base is manually assigned
at the end of the function to point to sdram. This code is outdated
as by now, the heap is switched to sdram by the common function
spl_relocate_stack_gd() if the appropriate defines are set.
As it was, the value assigned manually was directly overwritten by
this common code, so remove the manual assignment.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Simon Goldschmidt [Mon, 13 Aug 2018 07:33:44 +0000 (09:33 +0200)]
arm: socfpga: fix SPL on gen5 after moving to DM serial
There were NULL pointers dereferenced because DM was used
too early without correct initialization:
- malloc_simple returned NULL when called from preloader_console_init()
because gd->malloc_limit was 0
- uclass_add dereferenced gd->uclass_root members which were NULL because
dm_init (or one of its relatives) has not been called.
All this is fixed by calling spl_early_init before calling
preloader_console_init.
This fixes commit
73172753f4f3 ("ARM: socfpga: Convert to DM serial")
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Andre Przywara [Mon, 13 Aug 2018 11:10:08 +0000 (16:40 +0530)]
sunxi: A64: fix default DRAM_ODT_EN symbol
"default" lines in Kconfig are processed in order, the first hit will
stop considering subsequent lines. In the case of the DRAM_ODT_EN symbol
that means that everything following the first two lines will never be
checked:
------------
config DRAM_ODT_EN
bool "sunxi dram odt enable"
default n if !MACH_SUN8I_A23
default y if MACH_SUN8I_A23
default y if MACH_SUN8I_R40
default y if MACH_SUN50I
------------
Assuming that the "default y" for the A64 and the R40 were a deliberate
choice, fix the Kconfig stanza to take this into account.
Also remove the now redundant lines from the respective defconfigs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: droped 'default n' on original change]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # A64, R40
Tested-by: Chen-Yu Tsai <wens@csie.org> # A23
Jagan Teki [Sat, 4 Aug 2018 19:10:13 +0000 (00:40 +0530)]
ARM: dts: sun8i: Update R40/V40 dts(i) files from Linux-v4.18-rc3
Update all R40/V40 devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:
R40:
commit
c36fd5a48bd20820855e3e91a89297eeaa31836e
Author: Chen-Yu Tsai <wens@csie.org>
Date: Wed May 2 00:12:25 2018 +0800
ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable GMAC ethernet controller
V40:
commit
c5f0bb472795170ab5c33be12e29ce7465fb31ed
Author: Icenowy Zheng <icenowy@aosc.io>
Date: Fri Apr 6 22:03:44 2018 +0800
ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # BPI-M2-Ultra, BPI-M2-Berry
Jagan Teki [Sat, 4 Aug 2018 19:10:12 +0000 (00:40 +0530)]
ARM: dts: sun8i: Update A83T dts(i) files from Linux-v4.18-rc3
Update all A83T devicetree dtsi and dtsi files from Linux-v4.18-rc3
with below commit:
commit
221cb9fd2ee3042689fe0e6613d0f34eb46a5af6
Author: Mylène Josserand <mylene.josserand@bootlin.com>
Date: Fri May 4 21:05:44 2018 +0200
ARM: dts: sun8i: Add enable-method for SMP support for the A83T SoC
Note: bananapi-m3 and cubietruck-plus board dts files has
usb_otg enabled in U-Boot which were not present in Linux.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Sat, 11 Aug 2018 23:49:29 +0000 (19:49 -0400)]
Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-staging
Tom Rini [Sat, 11 Aug 2018 23:48:13 +0000 (19:48 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-video
Mario Six [Tue, 31 Jul 2018 12:24:15 +0000 (14:24 +0200)]
misc: Add gdsys_ioep driver
Add driver for the IHS IO endpoint on IHS FPGAs.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Tue, 31 Jul 2018 12:24:14 +0000 (14:24 +0200)]
test: Add tests for misc uclass
Add a set of tests for the misc uclass.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Mario Six [Tue, 31 Jul 2018 12:24:13 +0000 (14:24 +0200)]
misc: uclass: Add enable/disable function
Add generic enable/disable function to the misc uclass.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Tue, 31 Jul 2018 12:24:12 +0000 (14:24 +0200)]
misc: docs: Fix comments in misc.h
The comments in misc.h are not in kernel-doc format. Correct the format.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Thu, 9 Aug 2018 12:51:23 +0000 (14:51 +0200)]
video_display: Add Xilinx LogiCore DP TX
Add a driver for the Xilinx LogiCORE DisplayPort IP core, which is a
pure DP transmitter core for Xiling FPGA (no display capabilities).
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Thu, 9 Aug 2018 12:51:22 +0000 (14:51 +0200)]
video: Sort Makefile entries
The entries of Makefiles should be sorted, which is not the case in the
video driver Makefile.
Sort the entries alphabetically as far as this makes sense.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Thu, 9 Aug 2018 12:51:21 +0000 (14:51 +0200)]
cmd: Add axi command
Add a command to debug the AXI bus.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Thu, 9 Aug 2018 12:51:20 +0000 (14:51 +0200)]
test: Add AXI test
Add tests for the AXI uclass.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
Mario Six [Thu, 9 Aug 2018 12:51:19 +0000 (14:51 +0200)]
sandbox: Add and build AXI bus and device
Add test AXI drivers to the sandbox.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Mario Six <mario.six@gdsys.cc>