#define ANA_APB_ARM_MF_REG (ANA_REGS_GLB_PHYS + 0x110)
#define ANA_APB_AFUSE_CTL (ANA_REGS_GLB_PHYS + 0x114)
#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x118)
-#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x11C)
-#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x120)
-#define ANA_APB_AFUSE_OUT0 (ANA_REGS_GLB_PHYS + 0x124)
+#define ANA_APB_AFUSE_OUT1 (ANA_REGS_GLB_PHYS + 0x11C)
+#define ANA_APB_AFUSE_OUT2 (ANA_REGS_GLB_PHYS + 0x120)
+#define ANA_APB_AFUSE_OUT3 (ANA_REGS_GLB_PHYS + 0x124)
#define ANA_APB_ARCH_EN (ANA_REGS_GLB_PHYS + 0x128)
#define ANA_APB_MCU_WR_PROT_VAL (ANA_REGS_GLB_PHYS + 0x12C)
#define ANA_APB_DCDC_CORE (ANA_REGS_GLB_PHYS + 0x160)
#define SPRD_KPD_PHYS 0X40250000
#define SPRD_KPD_SIZE SZ_4K
+#ifdef SPRD_PWM_BASE
+#undef SPRD_PWM_BASE
+#endif
#define SPRD_PWM_BASE SCI_IOMAP(0x20a000)
#define SPRD_PWM_PHYS 0X40260000
#define SPRD_PWM_SIZE SZ_4K
#define ANA_CTL_GLB_BASE ( SPRD_MISC_BASE + 0x8800 )
+#ifdef ADC_BASE
+#undef ADC_BASE
+#endif
#define ADC_BASE ((unsigned int)SPRD_ADI_BASE + 0x8300)
#ifndef REGS_AHB_BASE
/**---------------------------------------------------------------------------*
** Micro Define **
**---------------------------------------------------------------------------*/
+#ifdef ANA_GPIO_BASE
+#undef ANA_GPIO_BASE
+#endif
#define ANA_GPIO_BASE SPRD_ANA_GPIO_PHYS
+#ifdef GPIO_BASE
+#undef GPIO_BASE
+#endif
#define GPIO_BASE SPRD_GPIO_PHYS
//GPIO_OFFSET
#define GPIO_DATA 0x0000 //GPIO data register
#include <asm/arch/adi_hal_internal.h>
/* set or clear the bit of register in reg_addr address */
+#ifdef REG_SETCLRBIT
+#undef REG_SETCLRBIT
+#endif
#define REG_SETCLRBIT(_reg_addr, _set_bit, _clr_bit) \
do { \
unsigned int reg_val = 0; \
#define REG_SETBIT(_reg_addr, _bit_mask, _bit_set) ANA_REG_MSK_OR(_reg_addr, _bit_set, _bit_mask);
/* macro used to get voltage level(one bit level) */
+#ifdef GET_LEVELBIT
+#undef GET_LEVELBIT
+#endif
#define GET_LEVELBIT(_reg_addr, _bit_mask, _bit_set, _level_var) \
do { \
(_level_var) |= \
} while (0)
/* macro used to get voltage level */
+#ifdef GET_LEVEL
+#undef GET_LEVEL
+#endif
#define GET_LEVEL(_reg_addr, _bit0_mask, _bit1_mask, _level_var) \
do { \
(_level_var) |= \
#include <asm/arch/bits.h>
#include <asm/arch/sprd_reg.h>
+#ifdef SPRD_ADI_BASE
+#undef SPRD_ADI_BASE
+#endif
#define SPRD_ADI_BASE SPRD_MISC_PHYS
#define ADI_CTL_REG (SPRD_ADI_BASE + 0x4 )
#define CHIP_TYPE 0x209003FC
#define AHB_CTL0 (AHB_REG_BASE + 0x00)
+#ifdef AHB_SOFT_RST
+#undef AHB_SOFT_RST
+#endif
#define AHB_SOFT_RST (AHB_REG_BASE + 0x04)
#define AHB_PAUSE (AHB_REG_BASE + 0x14)
#define AHB_REMAP (AHB_REG_BASE + 0x18)
#define DSP_BOOT_VEC (AHB_REG_BASE + 0x88)
#define DSP_RST (AHB_REG_BASE + 0x8C)
#define AHB_ENDIAN_EN (AHB_REG_BASE + 0x90)
+#ifdef USB_PHY_CTRL
+#undef USB_PHY_CTRL
+#endif
#define USB_PHY_CTRL (AHB_REG_BASE + 0xA0)
#define USB_SPR_REG (AHB_REG_BASE + 0xC0)
+#ifdef CHIP_ID
+#undef CHIP_ID
+#endif
#define CHIP_ID (AHB_REG_BASE + 0x1FC)
#define AHB_DSP_BOOT_EN (AHB_REG_BASE + 0x84)
#include <asm/arch/bits.h>
/*----------Global Registers----------*/
+#ifdef GREG_BASE
+#undef GREG_BASE
+#endif
#define GREG_BASE 0x4B000000
#define GR_GEN0 (GREG_BASE + 0x0008)
////
/*----------Real Timer Counter Register----------*/
///
+#ifdef RTC_BASE
+#undef RTC_BASE
+#endif
#define RTC_BASE SPRD_ANA_RTC_PHYS
#define ANA_RTC_SEC_CNT (RTC_BASE + 0x00)
#define ANA_RTC_MIN_CNT (RTC_BASE + 0x04)
#define KEY_INFO_SIZ (512)
#define CUSTOM_DATA_SIZ (1024)
#define VLR_INFO_SIZ (512)
-#define VLR_INFO_OFF (512)
#if defined(CONFIG_SPX30G)
#define INTER_RAM_BEGIN 0x50003000
#define EFUSE_BASE CTL_BASE_EFUSE
#define GPIO_BASE CTL_BASE_GPIO
#define PWM_BASE CTL_BASE_PWM
+#ifdef GREG_BASE
+#undef GREG_BASE
+#endif
#define GREG_BASE CTL_BASE_GLB_REG
#define WDG_BASE 0x40038040 //CHGR_WDG:0x820003C0 WDG:0x82000040
/*----------System Count----------*/
#include "sprd_reg.h"
+#ifdef SYSTIMER_BASE
+#undef SYSTIMER_BASE
+#endif
#define SYSTIMER_BASE (SPRD_SYSCNT_PHYS)
#define SYS_ALM (SYSTIMER_BASE + 0x0000)
/*----------Watchdog Timer Counter Register----------*/
#include "sprd_reg.h"
+#ifdef WDG_BASE
+#undef WDG_BASE
+#endif
#define WDG_BASE (SPRD_ANA_WDG_PHYS)
#define WDG_LOAD_LOW (WDG_BASE + 0x00)
#define WDG_LOAD_HIGH (WDG_BASE + 0x04)