the defaults discussed just above.
- Cache Configuration:
- CONFIG_SYS_ICACHE_OFF - Do not enable instruction cache in U-Boot
- CONFIG_SYS_DCACHE_OFF - Do not enable data cache in U-Boot
CONFIG_SYS_L2CACHE_OFF- Do not enable L2 cache in U-Boot
- Cache Configuration for ARM:
Build kernel for Big Endian Mode of ARC CPU
config SYS_ICACHE_OFF
- bool "Do not use Instruction Cache"
+ bool "Do not enable icache"
default n
+ help
+ Do not enable instruction cache in U-Boot.
config SYS_DCACHE_OFF
- bool "Do not use Data Cache"
+ bool "Do not enable dcache"
default n
+ help
+ Do not enable data cache in U-Boot.
menuconfig ARC_DBG
bool "ARC debugging"
config THUMB2_KERNEL
bool
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
config SYS_ARM_CACHE_CP15
bool "CP15 based cache enabling support"
help
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
-/*
- * Disable the dcache. Currently the network driver (mvgbe.c) and USB
- * EHCI driver (ehci-marvell.c) and possibly others rely on the data
- * cache being disabled.
- */
-#define CONFIG_SYS_DCACHE_OFF
/*
* By default kwbimage.cfg from board specific folder is used
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
source "board/AndesTech/adp-ag101p/Kconfig"
source "board/AndesTech/adp-ae3xx/Kconfig"
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
endchoice
+config SYS_ICACHE_OFF
+ bool "Do not enable icache"
+ default n
+ help
+ Do not enable instruction cache in U-Boot.
+
+config SYS_DCACHE_OFF
+ bool "Do not enable dcache"
+ default n
+ help
+ Do not enable data cache in U-Boot.
+
source "board/cadence/xtfpga/Kconfig"
endmenu
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFKW=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x00600000
CONFIG_TARGET_SBx81LIFXCAT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0xE80C0000
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
CONFIG_TARGET_BCM23550_W1D=y
CONFIG_SYS_TEXT_BASE=0x9f000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_COLIBRI_PXA270=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_NR_DRAM_BANKS=1
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x83F00000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DNS325=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DOCKSTAR=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DREAMPLUG=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_DS109=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ASPEED=y
CONFIG_SYS_TEXT_BASE=0x0
CONFIG_ASPEED_AST2500=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_FLEA3=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GOFLEXHOME=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_GPLUGD=y
CONFIG_SYS_TEXT_BASE=0x00f00000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_GURUPLUG=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_IB62X0=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_ICONNECT=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC0A0000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC200000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_SYS_TEXT_BASE=0xC000000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_ISW_ENTRY_ADDR=0xC100000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_LSXL=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NAS220=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NET2BIG_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NETSPACE_V2=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_NSA310S=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000
CONFIG_ARCH_EXYNOS4=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_TARGET_POGO_E02=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x07d00000
CONFIG_TARGET_KM_KIRKWOOD=y
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_KIRKWOOD=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_STV0991=y
CONFIG_SYS_TEXT_BASE=0x00010000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_WOODBURN=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ARM=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_WOODBURN_SD=y
CONFIG_SYS_TEXT_BASE=0x82000000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_ARM=y
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_LPC32XX=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_nand"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_qspi"
+CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x80
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0x100000
CONFIG_ENV_SIZE=0x190
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
CONFIG_ARM=y
CONFIG_SYS_CONFIG_NAME="zynq_cse"
+CONFIG_SYS_ICACHE_OFF=y
+CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_ZYNQ=y
CONFIG_SYS_TEXT_BASE=0xFFFC0000
CONFIG_ENV_SIZE=0x190
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
-#define CONFIG_SYS_DCACHE_OFF
/* STACK */
#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
-/* Enable cache controller */
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#ifdef CONFIG_PRE_CON_BUF_SZ
#define CONFIG_USBID_ADDR 0x34052c46
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_L2CACHE_OFF
#endif /* __BCM23550_W1D_H */
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT 0x40000
-/* We will never enable dcache because we have to setup MMU first */
-#define CONFIG_SYS_DCACHE_OFF
-
/*
* Environment settings
*/
#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
-#define CONFIG_SYS_DCACHE_OFF
-
#endif /* _CONFIG_DB_88F6281_BP_H */
#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/* High Level Configuration Options */
#define CONFIG_MX35
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* Set TEXT at the beginning of the NOR flash */
* Commands configuration
*/
-/* Disable DCACHE */
-#define CONFIG_SYS_DCACHE_OFF
-
/* Network configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_ARMADA100_FEC
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
#define CONFIG_SYS_TIMER_RATE (150000000/256)
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CONFIG_MALLOC_F_ADDR 0x182000
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
-#define CONFIG_SYS_DCACHE_OFF
-
/* ORIGEN has 4 bank of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
#ifndef __CONFIG_STV0991_H
#define __CONFIG_STV0991_H
-#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
/* ram memory-related information */
/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SPL_TARGET "u-boot-spi.gph"
-#define CONFIG_SYS_DCACHE_OFF
/* Memory Configuration */
#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
#define CONFIG_MX35_HCLK_FREQ 24000000
#define CONFIG_SYS_FSL_CLK
-#define CONFIG_SYS_DCACHE_OFF
-
#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
/* This is required to setup the ESDC controller */
*/
#define CONFIG_MACH_TYPE 736
-#define CONFIG_SYS_ICACHE_OFF
-#define CONFIG_SYS_DCACHE_OFF
#if !defined(CONFIG_SPL_BUILD)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
#ifndef __CONFIG_VERSAL_MINI_H
#define __CONFIG_VERSAL_MINI_H
-#define CONFIG_SYS_ICACHE_OFF
-
#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000
#define CONFIG_EXTRA_ENV_SETTINGS
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN 0x800000
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_SDRAM_SIZE 0x1000000
#define CONFIG_SYS_SDRAM_BASE 0x0
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000)
#include <configs/xilinx_zynqmp_mini.h>
-#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000)
#define CONFIG_SYS_MALLOC_LEN 0x2000
#define __CONFIG_ZYNQ_CSE_H
#define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_DCACHE_OFF
-#define CONFIG_SYS_ICACHE_OFF
#include <configs/zynq-common.h>