Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
  cleanups
- fsl-crypto: RNG support and bug fixes

diff --combined drivers/i2c/mxc_i2c.c
index 1a1de67,9e1bafc..e3d980a
--- 1/drivers/i2c/mxc_i2c.c
--- 2/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@@ -4,6 -4,7 +4,7 @@@
   *
   * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
+  * Copyright 2020 NXP
   *
   * Based on i2c-imx.c from linux kernel:
   *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
@@@ -341,6 -342,57 +342,57 @@@ static int i2c_init_transfer_(struct mx
        return 0;
  }
  
+ #if !defined(I2C2_BASE_ADDR)
+ #define I2C2_BASE_ADDR        0
+ #endif
+ 
+ #if !defined(I2C3_BASE_ADDR)
+ #define I2C3_BASE_ADDR        0
+ #endif
+ 
+ #if !defined(I2C4_BASE_ADDR)
+ #define I2C4_BASE_ADDR        0
+ #endif
+ 
+ #if !defined(I2C5_BASE_ADDR)
+ #define I2C5_BASE_ADDR 0
+ #endif
+ 
+ #if !defined(I2C6_BASE_ADDR)
+ #define I2C6_BASE_ADDR 0
+ #endif
+ 
+ #if !defined(I2C7_BASE_ADDR)
+ #define I2C7_BASE_ADDR 0
+ #endif
+ 
+ #if !defined(I2C8_BASE_ADDR)
+ #define I2C8_BASE_ADDR 0
+ #endif
+ 
+ static struct mxc_i2c_bus mxc_i2c_buses[] = {
+ #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
+       defined(CONFIG_FSL_LAYERSCAPE)
+       { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
+       { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
+ #else
+       { 0, I2C1_BASE_ADDR, 0 },
+       { 1, I2C2_BASE_ADDR, 0 },
+       { 2, I2C3_BASE_ADDR, 0 },
+       { 3, I2C4_BASE_ADDR, 0 },
+       { 4, I2C5_BASE_ADDR, 0 },
+       { 5, I2C6_BASE_ADDR, 0 },
+       { 6, I2C7_BASE_ADDR, 0 },
+       { 7, I2C8_BASE_ADDR, 0 },
+ #endif
+ };
+ 
  #ifndef CONFIG_DM_I2C
  int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  {
@@@ -434,6 -486,24 +486,24 @@@ exit
        return ret;
  }
  #endif
+ /*
+  * Early init I2C for prepare read the clk through I2C.
+  */
+ void i2c_early_init_f(void)
+ {
+       ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
+       bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
+                                       & I2C_QUIRK_FLAG ? true : false;
+       int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+ 
+       /* Set I2C divider value */
+       writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
+       /* Reset module */
+       writeb(I2CR_IDIS, base + (I2CR << reg_shift));
+       writeb(0, base + (I2SR << reg_shift));
+       /* Enable I2C */
+       writeb(I2CR_IEN, base + (I2CR << reg_shift));
+ }
  
  static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
                             u32 addr, int alen)
@@@ -662,57 -732,6 +732,6 @@@ static int bus_i2c_write(struct mxc_i2c
        return ret;
  }
  
- #if !defined(I2C2_BASE_ADDR)
- #define I2C2_BASE_ADDR        0
- #endif
- 
- #if !defined(I2C3_BASE_ADDR)
- #define I2C3_BASE_ADDR        0
- #endif
- 
- #if !defined(I2C4_BASE_ADDR)
- #define I2C4_BASE_ADDR        0
- #endif
- 
- #if !defined(I2C5_BASE_ADDR)
- #define I2C5_BASE_ADDR 0
- #endif
- 
- #if !defined(I2C6_BASE_ADDR)
- #define I2C6_BASE_ADDR 0
- #endif
- 
- #if !defined(I2C7_BASE_ADDR)
- #define I2C7_BASE_ADDR 0
- #endif
- 
- #if !defined(I2C8_BASE_ADDR)
- #define I2C8_BASE_ADDR 0
- #endif
- 
- static struct mxc_i2c_bus mxc_i2c_buses[] = {
- #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
-       defined(CONFIG_FSL_LAYERSCAPE)
-       { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
-       { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
- #else
-       { 0, I2C1_BASE_ADDR, 0 },
-       { 1, I2C2_BASE_ADDR, 0 },
-       { 2, I2C3_BASE_ADDR, 0 },
-       { 3, I2C4_BASE_ADDR, 0 },
-       { 4, I2C5_BASE_ADDR, 0 },
-       { 5, I2C6_BASE_ADDR, 0 },
-       { 6, I2C7_BASE_ADDR, 0 },
-       { 7, I2C8_BASE_ADDR, 0 },
- #endif
- };
- 
  struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
  {
        return &mxc_i2c_buses[adap->hwadapnr];
@@@ -778,24 -797,7 +797,7 @@@ void bus_i2c_init(int index, int speed
        bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
  }
  
- /*
-  * Early init I2C for prepare read the clk through I2C.
-  */
- void i2c_early_init_f(void)
- {
-       ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
-       bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
-                                       & I2C_QUIRK_FLAG ? true : false;
-       int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  
-       /* Set I2C divider value */
-       writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
-       /* Reset module */
-       writeb(I2CR_IDIS, base + (I2CR << reg_shift));
-       writeb(0, base + (I2SR << reg_shift));
-       /* Enable I2C */
-       writeb(I2CR_IEN, base + (I2CR << reg_shift));
- }
  
  /*
   * Init I2C Bus
@@@ -899,7 -901,7 +901,7 @@@ static int mxc_i2c_probe(struct udevic
  
        i2c_bus->driver_data = dev_get_driver_data(bus);
  
 -      addr = devfdt_get_addr(bus);
 +      addr = dev_read_addr(bus);
        if (addr == FDT_ADDR_T_NONE)
                return -EINVAL;
  

diff --combined drivers/spi/fsl_dspi.c
index 9396c38,c55ebee..b22c9b3
--- 1/drivers/spi/fsl_dspi.c
--- 2/drivers/spi/fsl_dspi.c
+++ b/drivers/spi/fsl_dspi.c
@@@ -9,6 -9,7 +9,7 @@@
   * Haikun Wang (B53464@freescale.com)
   */
  
+ #include <linux/math64.h>
  #include <common.h>
  #include <dm.h>
  #include <errno.h>
@@@ -25,6 -26,9 +26,9 @@@
  #include <linux/bitops.h>
  #include <linux/delay.h>
  
+ /* linux/include/time.h */
+ #define NSEC_PER_SEC  1000000000L
+ 
  DECLARE_GLOBAL_DATA_PTR;
  
  /* fsl_dspi_platdata flags */
@@@ -379,6 -383,40 +383,40 @@@ static int fsl_dspi_hz_to_spi_baud(int 
        return -EINVAL;
  }
  
+ static void ns_delay_scale(unsigned char *psc, unsigned char *sc, int delay_ns,
+                          unsigned long clkrate)
+ {
+       int scale_needed, scale, minscale = INT_MAX;
+       int pscale_tbl[4] = {1, 3, 5, 7};
+       u32 remainder;
+       int i, j;
+ 
+       scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
+                                  &remainder);
+       if (remainder)
+               scale_needed++;
+ 
+       for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
+               for (j = 0; j <= DSPI_CTAR_SCALE_BITS; j++) {
+                       scale = pscale_tbl[i] * (2 << j);
+                       if (scale >= scale_needed) {
+                               if (scale < minscale) {
+                                       minscale = scale;
+                                       *psc = i;
+                                       *sc = j;
+                               }
+                               break;
+                       }
+               }
+ 
+       if (minscale == INT_MAX) {
+               pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
+                       delay_ns, clkrate);
+               *psc = ARRAY_SIZE(pscale_tbl) - 1;
+               *sc = DSPI_CTAR_SCALE_BITS;
+       }
+ }
+ 
  static int fsl_dspi_cfg_speed(struct fsl_dspi_priv *priv, uint speed)
  {
        int ret;
@@@ -412,6 -450,9 +450,9 @@@ static int fsl_dspi_child_pre_probe(str
  {
        struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
        struct fsl_dspi_priv *priv = dev_get_priv(dev->parent);
+       u32 cs_sck_delay = 0, sck_cs_delay = 0;
+       unsigned char pcssck = 0, cssck = 0;
+       unsigned char pasc = 0, asc = 0;
  
        if (slave_plat->cs >= priv->num_chipselect) {
                debug("DSPI invalid chipselect number %d(max %d)!\n",
@@@ -419,7 -460,18 +460,18 @@@
                return -EINVAL;
        }
  
-       priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE;
+       ofnode_read_u32(dev->node, "fsl,spi-cs-sck-delay", &cs_sck_delay);
+       ofnode_read_u32(dev->node, "fsl,spi-sck-cs-delay", &sck_cs_delay);
+ 
+       /* Set PCS to SCK delay scale values */
+       ns_delay_scale(&pcssck, &cssck, cs_sck_delay, priv->bus_clk);
+ 
+       /* Set After SCK delay scale values */
+       ns_delay_scale(&pasc, &asc, sck_cs_delay, priv->bus_clk);
+ 
+       priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE |
+                                        DSPI_CTAR_PCSSCK(pcssck) |
+                                        DSPI_CTAR_PASC(pasc);
  
        debug("DSPI pre_probe slave device on CS %u, max_hz %u, mode 0x%x.\n",
              slave_plat->cs, slave_plat->max_hz, slave_plat->mode);
@@@ -534,7 -586,7 +586,7 @@@ static int fsl_dspi_ofdata_to_platdata(
        plat->num_chipselect =
                fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT);
  
 -      addr = devfdt_get_addr(bus);
 +      addr = dev_read_addr(bus);
        if (addr == FDT_ADDR_T_NONE) {
                debug("DSPI: Can't get base address or size\n");
                return -ENOMEM;

diff --combined scripts/config_whitelist.txt
index d4de735,d822abb..eee0e3a
--- 1/scripts/config_whitelist.txt
--- 2/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@@ -549,7 -549,6 +549,6 @@@ CONFIG_FSL_DIU_CH730
  CONFIG_FSL_DIU_FB
  CONFIG_FSL_DMA
  CONFIG_FSL_DSPI1
- CONFIG_FSL_ESDHC_ADAPTER_IDENT
  CONFIG_FSL_ESDHC_PIN_MUX
  CONFIG_FSL_FIXED_MMC_LOCATION
  CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
@@@ -4022,6 -4021,7 +4021,6 @@@ CONFIG_TSECV
  CONFIG_TSECV2_1
  CONFIG_TSEC_TBI
  CONFIG_TSEC_TBICR_SETTINGS
 -CONFIG_TULIP
  CONFIG_TWL6030_INPUT
  CONFIG_TWL6030_POWER
  CONFIG_TWR