#include <dt-bindings/clock/starfive-jh7110-vout.h>
#include <dt-bindings/clock/starfive-jh7110-isp.h>
#include <dt-bindings/power/jh7110-power.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "starfive,jh7110";
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imac";
tlb-split;
+ #cooling-cells = <2>;
status = "disabled";
cpu0intctrl: interrupt-controller {
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
next-level-cache = <&cachectrl>;
riscv,isa = "rv64imafdc";
tlb-split;
+ #cooling-cells = <2>;
status = "okay";
operating-points-v2 = <&cluster0_opp>;
thermal-sensors = <&sfctemp>;
- cooling-maps {
- };
-
trips {
cpu_alert0: cpu_alert0 {
/* milliCelsius */
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
+CONFIG_COMPILE_TEST=y
+# CONFIG_WERROR is not set
CONFIG_DEFAULT_HOSTNAME="StarFive"
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
CONFIG_PM_DEBUG=y
CONFIG_PM_ADVANCED_DEBUG=y
CONFIG_PM_TEST_SUSPEND=y
+CONFIG_ENERGY_MODEL=y
CONFIG_CPU_IDLE=y
CONFIG_RISCV_SBI_CPUIDLE=y
# CONFIG_SECCOMP is not set
CONFIG_POWER_RESET_SYSCON=y
CONFIG_POWER_RESET_SYSCON_POWEROFF=y
CONFIG_SENSORS_SFCTEMP=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_SYSFS=y
CONFIG_STARFIVE_WATCHDOG=y