pinctrl: starfive: jh7110: Correct the ioconfig register address and bit definitions

1. Correct the io_conf_reg address when pin number >= PAD_QSPI_SCLK.
2. The pull-down bit is the fourth bit, so the mask is 0x10.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

diff --git a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
index 06a8e21..2e057c6 100755 (executable)
--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7110.c
@@ -1064,8 +1064,10 @@ static void starfive_jh7110_sys_parse_pin_config(
        if (pin_data->pin < PAD_GMAC1_MDC) {
                pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
                        + SYS_GPO_PDA_0_74_CFG_BASE_REG;
-       } else if (pin_data->pin > PAD_GMAC1_TXC) {
-               pin_reg->io_conf_reg = (pin_data->pin * GPO_PDA_CFG_OFFSET)
+       } else if (pin_data->pin >= PAD_QSPI_SCLK &&
+                  pin_data->pin <= PAD_QSPI_DATA3) {
+               pin_reg->io_conf_reg =
+                       ((pin_data->pin - PAD_QSPI_SCLK) * GPO_PDA_CFG_OFFSET)
                        + SYS_GPO_PDA_89_94_CFG_BASE_REG;
        }
 

diff --git a/include/dt-bindings/pinctrl/starfive,jh7110-pinfunc.h b/include/dt-bindings/pinctrl/starfive,jh7110-pinfunc.h
index 83c523a..63a955b 100755 (executable)
--- a/include/dt-bindings/pinctrl/starfive,jh7110-pinfunc.h
+++ b/include/dt-bindings/pinctrl/starfive,jh7110-pinfunc.h
@@ -1560,7 +1560,7 @@
 #define GPIO_IE(data)           ((data << 0x0U) & 0x1U)
 #define GPIO_DS(data)           ((data << 0x1U) & 0x6U)
 #define GPIO_PU(data)           ((data << 0x3U) & 0x8U)
-#define GPIO_PD(data)           ((data << 0x4U) & 0x7U)
+#define GPIO_PD(data)           ((data << 0x4U) & 0x10U)
 #define GPIO_SLEW(data)         ((data << 0x5U) & 0x20U)
 #define GPIO_SMT(data)          ((data << 0x6U) & 0x40U)
 #define GPIO_POS(data)          ((data << 0x7U) & 0x80U)