moveconfig: prepare moving CONFIG_SYS_SPI_U_BOOT_OFFS to Kconfig step 2

[platform/kernel/u-boot.git] / include / configs / tao3530.h

diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index 4b596c6..c34e785 100644 (file)
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -23,8 +23,6 @@
 #define V_OSCK                 26000000        /* Clock output from T2 */
 #define V_SCLK                 (V_OSCK >> 1)
 
-#define CONFIG_MISC_INIT_R
-
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
@@ -34,7 +32,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN          (4 << 20)
-#define CONFIG_ENV_SIZE                        (128 << 10)     /* 128 KiB sector */
 
 /*
  * Hardware drivers
@@ -65,13 +62,10 @@
 /*
  * TWL4030
  */
-#define CONFIG_TWL4030_LED
 
 /*
  * Board NAND Info.
  */
-#define CONFIG_SYS_NAND_ADDR           NAND_BASE       /* physical address */
-                                                       /* to access nand */
 #define CONFIG_SYS_NAND_BASE           NAND_BASE       /* physical address */
                                                        /* to access nand at */
                                                        /* CS0 */
@@ -156,7 +150,6 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS   2       /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1           OMAP34XX_SDRC_CS0
 #define PHYS_SDRAM_1_SIZE      (32 << 20)      /* at least 32 MiB */
 #define PHYS_SDRAM_2           OMAP34XX_SDRC_CS1
@@ -176,7 +169,6 @@
 #define ONENAND_ENV_OFFSET             0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE       (128 << 10)
-#define CONFIG_ENV_OFFSET              0x260000
 #define CONFIG_ENV_ADDR                        CONFIG_ENV_OFFSET
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
@@ -225,7 +217,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    0x80000
 
-#define CONFIG_SPL_TEXT_BASE           0x40200800
 #define CONFIG_SPL_MAX_SIZE            (SRAM_SCRATCH_SPACE_ADDR - \
                                         CONFIG_SPL_TEXT_BASE)