Merge branch '2022-08-04-Kconfig-migrations'

[platform/kernel/u-boot.git] / include / configs / p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 6d417c5..f7d8723 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -78,14 +78,14 @@
 
 #ifdef CONFIG_SDCARD
 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST      (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START    (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS     (128 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MMC_U_BOOT_START    CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 #elif defined(CONFIG_SPIFLASH)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (128 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       CONFIG_SPL_PAD_TO
 #elif defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (832 << 10)
@@ -102,23 +102,16 @@
 #define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
 #endif
 
-#define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
-
 #define CONFIG_HWCONFIG
 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_L2_CACHE
 
-#define CONFIG_ENABLE_36BIT_PHYS
-
 #define CONFIG_SYS_CCSRBAR             0xffe00000
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_SPD_BUS_NUM 1
 #define SPD_EEPROM_ADDRESS 0x52
 
 #if defined(CONFIG_TARGET_P1020RDB_PD)
@@ -139,7 +132,6 @@
 #define CONFIG_SYS_DDR_CS1_CONFIG      0x80014302
 #define CONFIG_SYS_DDR_CS1_CONFIG_2    0x00000000
 
-#define CONFIG_SYS_DDR_DATA_INIT       0xdeadbeef
 #define CONFIG_SYS_DDR_INIT_ADDR       0x00000000
 #define CONFIG_SYS_DDR_INIT_EXT_ADDR   0x00000000
 #define CONFIG_SYS_DDR_MODE_CONTROL    0x00000000
@@ -173,7 +165,6 @@
  * 0xf8f8_0000 0xf8ff_ffff     L2 SRAM         Up to 512K cacheable
  *   (early boot only)
  * 0xff80_0000 0xff80_7fff     NAND flash      32K non-cacheable       CS1/0
- * 0xff98_0000 0xff98_ffff     PMC             64K non-cacheable       CS2
  * 0xffa0_0000 0xffaf_ffff     CPLD            1M non-cacheable        CS3
  * 0xffb0_0000 0xffbf_ffff     VSC7385 switch  1M non-cacheable        CS2
  * 0xffc0_0000 0xffc3_ffff     PCI IO range    256k non-cacheable
@@ -185,10 +176,8 @@
  * Local Bus Definitions
  */
 #if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_MAX_FLASH_SECT      512     /* 64M */
 #define CONFIG_SYS_FLASH_BASE          0xec000000
 #else
-#define CONFIG_SYS_MAX_FLASH_SECT      128     /* 16M */
 #define CONFIG_SYS_FLASH_BASE          0xef000000
 #endif
 
@@ -204,15 +193,8 @@
 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
 
 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45      /* count down from 45/5: 9..1 */
 
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
 /* Nand Flash */
 #ifdef CONFIG_NAND_FSL_ELBC
 #define CONFIG_SYS_NAND_BASE           0xff800000
@@ -280,14 +262,6 @@
 #endif
 /* CPLD config size: 1Mb */
 
-#define CONFIG_SYS_PMC_BASE    0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS       CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM   (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
-                                       BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM   (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
-                                OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
-                                OR_GPCM_EAD)
-
 /* Vsc7385 switch */
 #ifdef CONFIG_VSC7385_ENET
 #define __VSCFW_ADDR                   "vscfw_addr=ef000000\0"
@@ -357,8 +331,6 @@
 #define CONFIG_SYS_I2C_NOPROBES                { {0, 0x29} }
 #endif
 
-#define CONFIG_SYS_SPD_BUS_NUM         1 /* For rom_loc and flash bank */
-
 /*
  * I2C2 EEPROM
  */
@@ -402,8 +374,6 @@
 #else
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xffc00000
 #endif
-
-#define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -430,14 +400,10 @@
 /*
  * Environment
  */
-#if defined(CONFIG_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#elif defined(CONFIG_MTD_RAW_NAND)
+#if defined(CONFIG_MTD_RAW_NAND)
 #ifdef CONFIG_TPL_BUILD
 #define SPL_ENV_ADDR           (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
 #endif
-#elif defined(CONFIG_SYS_RAMBOOT)
-#define SPL_ENV_ADDR           (CONFIG_SYS_MONITOR_BASE - 0x1000)
 #endif
 
 #define CONFIG_LOADS_ECHO              /* echo on for serial download */
@@ -461,7 +427,6 @@
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ   (64 << 20)      /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
 /*
  * Environment Configuration