#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
-#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
#endif
/*
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
-#define CONFIG_SYS_L2_SIZE (256 << 10)
+#define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
/*
* Dynamic MTD Partition support with mtdparts
*/
#define __SW_NOR_BANK_MASK 0xfd
#define __SW_NOR_BANK_UP 0x00
#define __SW_NOR_BANK_LO 0x02
-#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */
+#define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */
+#define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */
/*
* Dynamic MTD Partition support with mtdparts
*/
#ifdef CONFIG_SDCARD
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST CONFIG_TEXT_BASE
+#define CONFIG_SYS_MMC_U_BOOT_START CONFIG_TEXT_BASE
+#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR
+#define CONFIG_SYS_MMC_U_BOOT_OFFS (CONFIG_SPL_PAD_TO - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA*512)
+#else
+#define CONFIG_SYS_MMC_U_BOOT_OFFS CONFIG_SPL_PAD_TO
+#endif
#elif defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
-#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST CONFIG_TEXT_BASE
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START CONFIG_TEXT_BASE
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#elif defined(CONFIG_MTD_RAW_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
* Local Bus Definitions
*/
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
#define CONFIG_SYS_FLASH_BASE 0xec000000
#else
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
#define CONFIG_SYS_FLASH_BASE 0xef000000
#endif
#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
/* Nand Flash */
#ifdef CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_BASE 0xff800000
#endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
#endif
#endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
-
#define CONFIG_SYS_CPLD_BASE 0xffa00000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
#endif
#endif
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
/*
* USB
*/
#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
"loadaddr=1000000\0" \
"bootfile=uImage\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE) " $filesize\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
MAP_NOR_LO_CMD(map_lowernorbank) \
MAP_NOR_UP_CMD(map_uppernorbank) \
RST_NOR_CMD(norboot) \
+RST_NOR_LO_CMD(norlowerboot) \
+RST_NOR_UP_CMD(norupperboot) \
RST_SPI_CMD(spiboot) \
RST_SD_CMD(sdboot) \
+RST_SD2_CMD(sd2boot) \
RST_NAND_CMD(nandboot) \
RST_PCIE_CMD(pciboot) \
+RST_DEF_CMD(defboot) \
""
#define CONFIG_USB_FAT_BOOT \