Convert CONFIG_SYS_MAX_NAND_DEVICE to Kconfig

[platform/kernel/u-boot.git] / include / configs / ls1088aqds.h

diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h
index 8923e32..d50b76b 100644 (file)
--- a/include/configs/ls1088aqds.h
+++ b/include/configs/ls1088aqds.h
@@ -8,33 +8,14 @@
 
 #include "ls1088a_common.h"
 
-
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
-#ifdef CONFIG_TFABOOT
-#define CONFIG_MISC_INIT_R
-#endif
-
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
-#define CONFIG_QIXIS_I2C_ACCESS
 #define SYS_NO_FLASH
-
-#define CONFIG_SYS_CLK_FREQ            100000000
-#else
-#define CONFIG_QIXIS_I2C_ACCESS
-#define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #endif
 
-#define COUNTER_FREQUENCY_REAL         (CONFIG_SYS_CLK_FREQ/4)
-#define COUNTER_FREQUENCY              25000000        /* 25MHz */
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR     1
+#define COUNTER_FREQUENCY_REAL         (get_board_sys_clk()/4)
 
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 #define SPD_EEPROM_ADDRESS             0x51
-#define CONFIG_SYS_SPD_BUS_NUM         0
 
 
 /*
@@ -81,15 +62,8 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
 #ifndef SYS_NO_FLASH
-#define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
-#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE,\
                                         CONFIG_SYS_FLASH_BASE + 0x40000000}
 #endif
@@ -128,10 +102,8 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_NAND_FTIM3          0x0
 
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
-#define CONFIG_FSL_QIXIS
 #define CONFIG_SYS_I2C_FPGA_ADDR       0x66
 #define QIXIS_LBMAP_SWITCH             6
 #define QIXIS_QMAP_MASK                        0xe0
@@ -302,16 +274,10 @@ unsigned long get_board_sys_clk(void);
 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 #define I2C_SVDD_MONITOR_ADDR           0x4F
 
-#define CONFIG_VID_FLS_ENV              "ls1088aqds_vdd_mv"
-#define CONFIG_VID
-
 /* The lowest and highest voltage allowed for LS1088AQDS */
 #define VDD_MV_MIN                     819
 #define VDD_MV_MAX                     1212
 
-#define CONFIG_VOL_MONITOR_LTC3882_SET
-#define CONFIG_VOL_MONITOR_LTC3882_READ
-
 #define PWM_CHANNEL0                    0x0
 
 /*
@@ -320,31 +286,12 @@ unsigned long get_board_sys_clk(void);
 #define RTC
 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_NXID
-#define CONFIG_SYS_EEPROM_BUS_NUM              0
-
 #ifdef CONFIG_FSL_DSPI
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_SPI_FLASH_SST
-#define CONFIG_SPI_FLASH_EON
 #if !defined(CONFIG_TFABOOT) && \
        !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #endif
 #endif
 
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#endif
-
-#define CONFIG_FSL_MEMAC
-
-/*  MMC  */
-#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
-       QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
-
 #define COMMON_ENV \
        "kernelheader_addr_r=0x80200000\0"      \
        "fdtheader_addr_r=0x80100000\0"         \
@@ -513,7 +460,6 @@ unsigned long get_board_sys_clk(void);
 #endif
 
 #ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_FSL_MEMAC
 #define RGMII_PHY1_ADDR                0x1
 #define RGMII_PHY2_ADDR                0x2
 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
@@ -538,9 +484,6 @@ unsigned long get_board_sys_clk(void);
 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
 
-#define CONFIG_ETHPRIME                "DPMAC1@xgmii"
-#define CONFIG_PHY_GIGE                /* Include GbE speed/duplex detection */
-
 #endif
 
 #define BOOT_TARGET_DEVICES(func) \