Fix problems with SNTP support;

[platform/kernel/u-boot.git] / include / configs / cmc_pu2.h

diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index e87e318..34efc38 100644 (file)
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -1,5 +1,5 @@
 /*
- * Gary Jennejohn <garyj@denx.de>
+ * 2004-2005 Gary Jennejohn <garyj@denx.de>
  *
  * Configuration settings for the CMC PU2 board.
  *
@@ -52,6 +52,38 @@
 #define CONFIG_BOOTBINFUNC
 #endif
 
+#ifdef CONFIG_BOOTBINFUNC
+#define CFG_USE_MAIN_OSCILLATOR                1
+/* flash */
+#define MC_PUIA_VAL    0x00000000
+#define MC_PUP_VAL     0x00000000
+#define MC_PUER_VAL    0x00000000
+#define MC_ASR_VAL     0x00000000
+#define MC_AASR_VAL    0x00000000
+#define EBI_CFGR_VAL   0x00000000
+#define SMC2_CSR_VAL   0x100032ad /* 16bit, 2 TDF, 4 WS */
+
+/* clocks */
+#define PLLAR_VAL      0x202CBE04 /* 207.360 MHz for PCK */
+#define PLLBR_VAL      0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
+#define MCKR_VAL       0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */
+
+/* sdram */
+#define PIOC_ASR_VAL   0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
+#define PIOC_BSR_VAL   0x00000000
+#define PIOC_PDR_VAL   0xFFFF0000
+#define EBI_CSA_VAL    0x00000002 /* CS1=SDRAM */
+#define SDRC_CR_VAL    0x3399c1d4 /* set up the SDRAM */
+#define SDRAM          0x20000000 /* address of the SDRAM */
+#define SDRAM1         0x20000080 /* address of the SDRAM */
+#define SDRAM_VAL      0x00000000 /* value written to SDRAM */
+#define SDRC_MR_VAL    0x00000002 /* Precharge All */
+#define SDRC_MR_VAL1   0x00000004 /* refresh */
+#define SDRC_MR_VAL2   0x00000003 /* Load Mode Register */
+#define SDRC_MR_VAL3   0x00000000 /* Normal Mode */
+#define SDRC_TR_VAL    0x000002E0 /* Write refresh rate */
+#endif
+
 /*
  * Size of malloc() pool
  */
@@ -94,15 +126,19 @@
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_COMMANDS                \
                       ((CONFIG_CMD_DFL | \
-                       CFG_CMD_I2C     | \
                        CFG_CMD_DATE    | \
+                       CFG_CMD_DHCP    | \
                        CFG_CMD_EEPROM  | \
-                       CFG_CMD_DHCP )  & \
+                       CFG_CMD_I2C     | \
+                       CFG_CMD_NFS     | \
+                       CFG_CMD_SNTP  ) & \
                      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
 #else
 #define CONFIG_COMMANDS                \
                       ((CONFIG_CMD_DFL | \
-                       CFG_CMD_DHCP )  & \
+                       CFG_CMD_DHCP    | \
+                       CFG_CMD_NFS     | \
+                       CFG_CMD_SNTP  ) & \
                      ~(CFG_CMD_FPGA | CFG_CMD_MISC) )
 #define CONFIG_TIMESTAMP
 #endif
@@ -138,8 +174,8 @@
 #define CFG_MONITOR_BASE               CFG_FLASH_BASE
 #define CFG_MAX_FLASH_BANKS            1
 #define CFG_MAX_FLASH_SECT             256
-#define CFG_FLASH_ERASE_TOUT           (2*CFG_HZ) /* Timeout for Flash Erase */
-#define CFG_FLASH_WRITE_TOUT           (2*CFG_HZ) /* Timeout for Flash Write */
+#define CFG_FLASH_ERASE_TOUT           (11 * CFG_HZ)   /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT           ( 2 * CFG_HZ)   /* Timeout for Flash Write */
 
 #define CFG_ENV_IS_IN_FLASH            1
 #define CFG_ENV_OFFSET                 0x20000         /* after u-boot.bin */