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Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE
[platform/kernel/u-boot.git] / include / configs / MPC8641HPCN.h
diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h
index a46f7c8..a46ec28 100644 (file)
--- a/include/configs/MPC8641HPCN.h
+++ b/include/configs/MPC8641HPCN.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2006 Freescale Semiconductor.
+ * Copyright 2006, 2010 Freescale Semiconductor.
  *
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
@@ -58,8 +58,8 @@
 
 #ifndef CONFIG_RIO                     /* RIO/PCI are mutually exclusive */
 #define CONFIG_PCI             1       /* Enable PCI/PCIE */
-#define CONFIG_PCI1            1       /* PCIE controler 1 (ULI bridge) */
-#define CONFIG_PCI2            1       /* PCIE controler 2 (slot) */
+#define CONFIG_PCIE1           1       /* PCIE controler 1 (ULI bridge) */
+#define CONFIG_PCIE2           1       /* PCIE controler 2 (slot) */
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 #endif
@@ -68,6 +68,7 @@
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
+#define CONFIG_BAT_RW          1       /* Use common BAT rw code */
 #define CONFIG_HIGH_BATS       1       /* High BATs supported and enabled */
 #define CONFIG_SYS_NUM_ADDR_MAP 8      /* Number of addr map slots = 8 dbats */
 
@@ -122,8 +123,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR_PHYS_LOW
 #endif
 
-#define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR           (CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_HWCONFIG        /* use hwconfig to control memory interleaving */
 
 /*
  * DDR Setup
@@ -239,7 +239,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE       /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE    /* start of monitor */
 #define CONFIG_SYS_MONITOR_BASE_EARLY   0xfff00000     /* early monitor loc */
 
 #define CONFIG_FLASH_CFI_DRIVER
@@ -276,7 +276,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    1
@@ -301,10 +300,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_OF_BOARD_SETUP          1
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
-
-#define CONFIG_SYS_64BIT_VSPRINTF      1
-#define CONFIG_SYS_64BIT_STRTOUL       1
-
 /*
  * I2C
  */
@@ -332,43 +327,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * Addresses are mapped 1-1.
  */
 
-#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS                0xe0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       0x0000000c00000000ULL
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0x0000000c00000000ULL
 #else
-#define CONFIG_SYS_PCI1_MEM_BUS                CONFIG_SYS_PCI1_MEM_VIRT
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_BUS       CONFIG_SYS_PCIE1_MEM_VIRT
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_VIRT
 #endif
-#define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI1_IO_VIRT        0xffc00000
-#define CONFIG_SYS_PCI1_IO_PHYS        (CONFIG_SYS_PCI1_IO_VIRT \
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xffc00000
+#define CONFIG_SYS_PCIE1_IO_PHYS       (CONFIG_SYS_PCIE1_IO_VIRT \
                                 | CONFIG_SYS_PHYS_ADDR_HIGH)
-#define CONFIG_SYS_PCI1_IO_SIZE        0x00010000      /* 64K */
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64K */
 
 #ifdef CONFIG_PHYS_64BIT
 /*
- * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT.
+ * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
  * This will increase the amount of PCI address space available for
  * for mapping RAM.
  */
-#define CONFIG_SYS_PCI2_MEM_BUS                CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCIE2_MEM_BUS       CONFIG_SYS_PCIE1_MEM_BUS
 #else
-#define CONFIG_SYS_PCI2_MEM_BUS                (CONFIG_SYS_PCI1_MEM_BUS \
-                                        + CONFIG_SYS_PCI1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_BUS       (CONFIG_SYS_PCIE1_MEM_BUS \
+                                        + CONFIG_SYS_PCIE1_MEM_SIZE)
 #endif
-#define CONFIG_SYS_PCI2_MEM_VIRT       (CONFIG_SYS_PCI1_MEM_VIRT \
-                                        + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_PHYS       (CONFIG_SYS_PCI1_MEM_PHYS \
-                                        + CONFIG_SYS_PCI1_MEM_SIZE)
-#define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
-                                + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_PHYS        (CONFIG_SYS_PCI1_IO_PHYS \
-                                + CONFIG_SYS_PCI1_IO_SIZE)
-#define CONFIG_SYS_PCI2_IO_SIZE        CONFIG_SYS_PCI1_IO_SIZE
+#define CONFIG_SYS_PCIE2_MEM_VIRT      (CONFIG_SYS_PCIE1_MEM_VIRT \
+                                        + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_PHYS      (CONFIG_SYS_PCIE1_MEM_PHYS \
+                                        + CONFIG_SYS_PCIE1_MEM_SIZE)
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#define CONFIG_SYS_PCIE2_IO_VIRT       (CONFIG_SYS_PCIE1_IO_VIRT \
+                                        + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_PHYS       (CONFIG_SYS_PCIE1_IO_PHYS \
+                                        + CONFIG_SYS_PCIE1_IO_SIZE)
+#define CONFIG_SYS_PCIE2_IO_SIZE       CONFIG_SYS_PCIE1_IO_SIZE
 
 #if defined(CONFIG_PCI)
 
@@ -397,10 +392,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS        1
 
 /*PCIE video card used*/
-#define VIDEO_IO_OFFSET                CONFIG_SYS_PCI2_IO_VIRT
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE2_IO_VIRT
 
 /*PCI video card used*/
-/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCI1_IO_VIRT*/
+/*#define VIDEO_IO_OFFSET      CONFIG_SYS_PCIE1_IO_VIRT*/
 
 /* video */
 #define CONFIG_VIDEO
@@ -413,7 +408,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_ATI_RADEON_FB
 #define CONFIG_VIDEO_LOGO
 /*#define CONFIG_CONSOLE_CURSOR*/
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
@@ -429,8 +424,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_SCSI_MAXDEVICE      CONFIG_SYS_SCSI_MAX_DEVICE
 #endif
 
-#define CONFIG_MPC86XX_PCI2
-
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -486,9 +479,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  * BAT0                DDR
  */
 #define CONFIG_SYS_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U      CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
 
 /*
  * BAT1                LBC (PIXIS/CF)
@@ -503,17 +494,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_IBAT1U      CONFIG_SYS_DBAT1U
 
 /* if CONFIG_PCI:
- * BAT2                PCI1 and PCI1 MEM
+ * BAT2                PCIE1 and PCIE1 MEM
  * if CONFIG_RIO
  * BAT2                Rapidio Memory
  */
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_DBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+#define CONFIG_SYS_DBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT \
                                 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \
+#define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
                                 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
+#define CONFIG_SYS_IBAT2L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U      CONFIG_SYS_DBAT2U
 #else /* CONFIG_RIO */
@@ -562,14 +553,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 
 /*
- * BAT4                PCI1_IO and PCI2_IO
+ * BAT4                PCIE1_IO and PCIE2_IO
  */
-#define CONFIG_SYS_DBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+#define CONFIG_SYS_DBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT \
                                 | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT4U      (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
+#define CONFIG_SYS_DBAT4U      (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
                                 | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
+#define CONFIG_SYS_IBAT4L      (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \
                                 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT4U      CONFIG_SYS_DBAT4U
 
@@ -596,7 +587,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 /* Map the last 1M of flash where we're running from reset */
 #define CONFIG_SYS_DBAT6L_EARLY        (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
                                 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT6U_EARLY        (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT6U_EARLY        (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT6L_EARLY        (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
                                 | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U_EARLY        CONFIG_SYS_DBAT6U_EARLY
@@ -737,11 +728,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
        "netdev=eth0\0"                                                 \
        "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"                          \
        "tftpflash=tftpboot $loadaddr $uboot; "                         \
-               "protect off " MK_STR(TEXT_BASE) " +$filesize; "        \
-               "erase " MK_STR(TEXT_BASE) " +$filesize; "              \
-               "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "      \
-               "protect on " MK_STR(TEXT_BASE) " +$filesize; "         \
-               "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"     \
+               "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "     \
+               "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "           \
+               "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "   \
+               "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "              \
+               "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"  \
        "consoledev=ttyS0\0"                                            \
        "ramdiskaddr=2000000\0"                                         \
        "ramdiskfile=your.ramdisk.u-boot\0"                             \
Domain: System / Kernel;