#define CONFIG_QE 1 /* Has QE */
/*
- * Hardware Reset Configuration Word
- */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_2X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CSB_TO_CLKIN_2X1 |\
- HRCWL_CORE_TO_CSB_2_5X1 |\
- HRCWL_CE_PLL_VCO_DIV_2 |\
- HRCWL_CE_PLL_DIV_1X1 |\
- HRCWL_CE_TO_PLL_1X3)
-
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_BIG_ENDIAN |\
- HRCWH_LALE_NORMAL)
-
-/*
* System IO Config
*/
#define CONFIG_SYS_SICRL 0x00000000