Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE

[platform/kernel/u-boot.git] / include / configs / M54451EVB.h

diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index cc57da8..1ff80ee 100644 (file)
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -94,7 +94,7 @@
 #      define MCFFEC_TOUT_LOOP 50000
 
 #      define CONFIG_BOOTDELAY 1       /* autoboot after 5 seconds */
-#      define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
+#      define CONFIG_BOOTARGS          "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
 #      define CONFIG_ETHADDR           00:e0:0c:bc:e5:60
 #      define CONFIG_ETHPRIME          "FEC0"
 #      define CONFIG_IPADDR            192.162.1.2
@@ -167,26 +167,24 @@
 #define CONFIG_SYS_IMMR                        CONFIG_SYS_MBAR
 
 /* DSPI and Serial Flash */
+#define CONFIG_CF_SPI
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
 #define CONFIG_HARD_SPI
-#define CONFIG_SYS_SER_FLASH_BASE      0x01000000
 #define CONFIG_SYS_SBFHDR_SIZE         0x7
 #ifdef CONFIG_CMD_SPI
 #      define CONFIG_SPI_FLASH
 #      define CONFIG_SPI_FLASH_STMICRO
 
-#      define CONFIG_SYS_DSPI_DCTAR0   (DSPI_DCTAR_TRSZ(7) | \
-                                        DSPI_DCTAR_CPOL | \
-                                        DSPI_DCTAR_CPHA | \
-                                        DSPI_DCTAR_PCSSCK_1CLK | \
-                                        DSPI_DCTAR_PASC(0) | \
-                                        DSPI_DCTAR_PDT(0) | \
-                                        DSPI_DCTAR_CSSCK(0) | \
-                                        DSPI_DCTAR_ASC(0) | \
-                                        DSPI_DCTAR_PBR(0) | \
-                                        DSPI_DCTAR_DT(1) | \
-                                        DSPI_DCTAR_BR(1))
+#      define CONFIG_SYS_DSPI_CTAR0    (DSPI_CTAR_TRSZ(7) | \
+                                        DSPI_CTAR_PCSSCK_1CLK | \
+                                        DSPI_CTAR_PASC(0) | \
+                                        DSPI_CTAR_PDT(0) | \
+                                        DSPI_CTAR_CSSCK(0) | \
+                                        DSPI_CTAR_ASC(0) | \
+                                        DSPI_CTAR_DT(1))
+#      define CONFIG_SYS_DSPI_CTAR1    (CONFIG_SYS_DSPI_CTAR0)
+#      define CONFIG_SYS_DSPI_CTAR2    (CONFIG_SYS_DSPI_CTAR0)
 #endif
 
 /* Input, PCI, Flexbus, and VCO */
@@ -247,7 +245,7 @@
 #define CONFIG_SYS_MEMTEST_END         ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 
 #ifdef CONFIG_CF_SBF
-#      define CONFIG_SYS_MONITOR_BASE  (TEXT_BASE + 0x400)
+#      define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_TEXT_BASE + 0x400)
 #else
 #      define CONFIG_SYS_MONITOR_BASE  (CONFIG_SYS_FLASH_BASE + 0x400)
 #endif
@@ -279,20 +277,9 @@
 #      define CONFIG_ENV_SECT_SIZE     0x8000
 #endif
 #undef CONFIG_ENV_OVERWRITE
-#undef CONFIG_ENV_IS_EMBEDDED
 
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#ifdef CONFIG_SYS_STMICRO_BOOT
-#      define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_SER_FLASH_BASE
-#      define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_SER_FLASH_BASE
-#      define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_CS0_BASE
-#else
-#      define CONFIG_SYS_FLASH_BASE            CONFIG_SYS_CS0_BASE
-#      define CONFIG_SYS_FLASH0_BASE           CONFIG_SYS_CS0_BASE
-#      define CONFIG_SYS_FLASH1_BASE           CONFIG_SYS_SER_FLASH_BASE
-#endif
+/* FLASH organization */
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
 
 #define CONFIG_SYS_FLASH_CFI
 #ifdef CONFIG_SYS_FLASH_CFI
@@ -322,6 +309,21 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE              16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_IEC | \
+                                        CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
+                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
+                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */