config BITBANGMII
bool "Bit-banged ethernet MII management channel support"
+config BITBANGMII_MULTI
+ bool "Enable the multi bus support"
+ depends on BITBANGMII
+
config MV88E6352_SWITCH
bool "Marvell 88E6352 switch support"
config PHYLIB_10G
bool "Generic 10G PHY support"
+config PHY_ADIN
+ bool "Analog Devices Industrial Ethernet PHYs"
+ help
+ Add support for configuring RGMII on Analog Devices ADIN PHYs.
+
menuconfig PHY_AQUANTIA
bool "Aquantia Ethernet PHYs support"
select PHY_GIGE
config PHY_AQUANTIA_UPLOAD_FW
bool "Aquantia firmware loading support"
- default n
depends on PHY_AQUANTIA
help
Aquantia PHYs use firmware which can be either loaded automatically
config PHY_CORTINA
bool "Cortina Ethernet PHYs support"
+config SYS_CORTINA_NO_FW_UPLOAD
+ bool "Cortina firmware loading support"
+ depends on PHY_CORTINA
+ help
+ Cortina phy has provision to store phy firmware in attached dedicated
+ EEPROM. And boards designed with such EEPROM does not require firmware
+ upload.
+
choice
prompt "Location of the Cortina firmware"
default SYS_CORTINA_FW_IN_NOR
endchoice
+config CORTINA_FW_ADDR
+ hex "Cortina Firmware Address"
+ depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
+ default 0x0
+
+config CORTINA_FW_LENGTH
+ hex "Cortina Firmware Length"
+ depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
+ default 0x40000
+
+config PHY_CORTINA_ACCESS
+ bool "Cortina Access Ethernet PHYs support"
+ default y
+ depends on CORTINA_NI_ENET
+ help
+ Cortina Access Ethernet PHYs init process
+
config PHY_DAVICOM
bool "Davicom Ethernet PHYs support"
config PHY_NATSEMI
bool "National Semiconductor Ethernet PHYs support"
-config PHY_REALTEK
- bool "Realtek Ethernet PHYs support"
+config PHY_NXP_C45_TJA11XX
+ tristate "NXP C45 TJA11XX PHYs"
+ help
+ Enable support for NXP C45 TJA11XX PHYs.
+ Currently supports only the TJA1103 PHY.
-config RTL8211E_PINE64_GIGABIT_FIX
- bool "Fix gigabit throughput on some Pine64+ models"
- depends on PHY_REALTEK
+config PHY_NXP_TJA11XX
+ bool "NXP TJA11XX Ethernet PHYs support"
help
- Configure the Realtek RTL8211E found on some Pine64+ models differently to
- fix throughput on Gigabit links, turning off all internal delays in the
- process. The settings that this touches are not documented in the CONFREG
- section of the RTL8211E datasheet, but come from Realtek by way of the
- Pine64 engineering team.
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
+config PHY_REALTEK
+ bool "Realtek Ethernet PHYs support"
config RTL8211X_PHY_FORCE_MASTER
bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
config RTL8211F_PHY_FORCE_EEE_RXC_ON
bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
depends on PHY_REALTEK
- default n
help
The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
transitions to/from a lower power consumption level (Low Power Idle
Default n, which means that the PHY state is not changed. To work
around the issues, change this setting to y.
+config RTL8201F_PHY_S700_RMII_TIMINGS
+ bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
+ depends on PHY_REALTEK
+ help
+ This provides an option to configure specific timing requirements (needed
+ for proper PHY operations) for the PHY module present on ACTION SEMI S700
+ based cubieboard7. Exact timing requiremnets seems to be SoC specific
+ (and it's undocumented) that comes from vendor code itself.
+
config PHY_SMSC
bool "Microchip(SMSC) Ethernet PHYs support"
---help---
Adds support for the TI DP83867 1Gbit PHY.
+config PHY_TI_DP83869
+ select PHY_TI
+ bool "Texas Instruments Ethernet DP83869 PHY support"
+ ---help---
+ Adds support for the TI DP83869 1Gbit PHY.
+
config PHY_TI_GENERIC
select PHY_TI
bool "Texas Instruments Generic Ethernet PHYs support"
config PHY_XILINX_GMII2RGMII
bool "Xilinx GMII to RGMII Ethernet PHYs support"
+ depends on DM_ETH
help
This adds support for Xilinx GMII to RGMII IP core. This IP acts
as bridge between MAC connected over GMII and external phy that
is connected over RGMII interface.
+config PHY_ETHERNET_ID
+ bool "Read ethernet PHY id"
+ depends on DM_GPIO
+ default y if ZYNQ_GEM
+ help
+ Enable this config to read ethernet phy id from the phy node of DT
+ and create a phy device using id.
+
config PHY_FIXED
bool "Fixed-Link PHY"
depends on DM_ETH
depends on DM_ETH
endif #PHYLIB
+
+config FSL_MEMAC
+ bool "NXP mEMAC PHY support"
+
+config SYS_MEMAC_LITTLE_ENDIAN
+ bool "mEMAC is access in little endian mode"
+ depends on FSL_MEMAC || FSL_LS_MDIO
+
+config PHY_RESET_DELAY
+ int "Extra delay after reset before MII register access"
+ default 0
+ help
+ Some PHYs need extra delay after reset before any MII register access
+ is possible. For such PHY, set this option to the usec delay
+ required.
projects / platform / kernel / u-boot.git / blobdiff