vf610twr: Fix typo in DRAM init

[platform/kernel/u-boot.git] / doc / README.x86

diff --git a/doc/README.x86 b/doc/README.x86
index 9012541..6cf293b 100644 (file)
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -189,7 +189,7 @@ Offset   Description         Controlling config
 001000   me.bin              Set by the descriptor
 500000   <spare>
 700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
-790000   vga.bin             CONFIG_X86_OPTION_ROM_ADDR
+790000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
 7fe000   Environment         CONFIG_ENV_OFFSET
@@ -245,10 +245,10 @@ this capability yet. The command is as follows:
 
 # in the coreboot root directory
 $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
-  -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
+  -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
 
-Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
-symbol address of _start (in arch/x86/cpu/start.S).
+Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
+of _x86boot_start (in arch/x86/cpu/start.S).
 
 If you want to use ELF as the coreboot payload, change U-Boot configuration to
 use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
@@ -654,13 +654,13 @@ Use the device tree for configuration where possible.
 For the microcode you can create a suitable device tree file using the
 microcode tool:
 
-  ./tools/microcode-tool -d microcode.dat create <model>
+  ./tools/microcode-tool -d microcode.dat -m <model> create
 
 or if you only have header files and not the full Intel microcode.dat database:
 
   ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
        -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
-       create all
+       -m all create
 
 These are written to arch/x86/dts/microcode/ by default.
 
@@ -718,11 +718,51 @@ allocation and assignment will be done by U-Boot automatically. Now you can
 enable CONFIG_GENERATE_PIRQ_TABLE for testing Linux kernel using i8259 PIC and
 CONFIG_GENERATE_MP_TABLE for testing Linux kernel using local APIC and I/O APIC.
 
+This script might be useful. If you feed it the output of 'pci long' from
+U-Boot then it will generate a device tree fragment with the interrupt
+configuration for each device (note it needs gawk 4.0.0):
+
+   $ cat console_output |awk '/PCI/ {device=$4} /interrupt line/ {line=$4} \
+       /interrupt pin/ {pin = $4; if (pin != "0x00" && pin != "0xff") \
+       {patsplit(device, bdf, "[0-9a-f]+"); \
+       printf "PCI_BDF(%d, %d, %d) INT%c PIRQ%c\n", strtonum("0x" bdf[1]), \
+       strtonum("0x" bdf[2]), bdf[3], strtonum(pin) + 64, 64 + strtonum(pin)}}'
+
+Example output:
+   PCI_BDF(0, 2, 0) INTA PIRQA
+   PCI_BDF(0, 3, 0) INTA PIRQA
+...
+
+Porting Hints
+-------------
+
+Quark-specific considerations:
+
+To port U-Boot to other boards based on the Intel Quark SoC, a few things need
+to be taken care of. The first important part is the Memory Reference Code (MRC)
+parameters. Quark MRC supports memory-down configuration only. All these MRC
+parameters are supplied via the board device tree. To get started, first copy
+the MRC section of arch/x86/dts/galileo.dts to your board's device tree, then
+change these values by consulting board manuals or your hardware vendor.
+Available MRC parameter values are listed in include/dt-bindings/mrc/quark.h.
+The other tricky part is with PCIe. Quark SoC integrates two PCIe root ports,
+but by default they are held in reset after power on. In U-Boot, PCIe
+initialization is properly handled as per Quark's firmware writer guide.
+In your board support codes, you need provide two routines to aid PCIe
+initialization, which are board_assert_perst() and board_deassert_perst().
+The two routines need implement a board-specific mechanism to assert/deassert
+PCIe PERST# pin. Care must be taken that in those routines that any APIs that
+may trigger PCI enumeration process are strictly forbidden, as any access to
+PCIe root port's configuration registers will cause system hang while it is
+held in reset. For more details, check how they are implemented by the Intel
+Galileo board support codes in board/intel/galileo/galileo.c.
+
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
 - SMI and ACPI support, to provide platform info and facilities to Linux
+- Desktop Management Interface (DMI) [15] support
 
 References
 ----------
@@ -740,3 +780,4 @@ References
 [12] http://events.linuxfoundation.org/sites/events/files/slides/chromeos_and_diy_vboot_0.pdf
 [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf
 [14] doc/device-tree-bindings/misc/intel,irq-router.txt
+[15] http://en.wikipedia.org/wiki/Desktop_Management_Interface