MPC5xxx: Change names of defines related to IPB and PCI clocks.

[platform/kernel/u-boot.git] / cpu / mpc5xxx / cpu_init.c

diff --git a/cpu/mpc5xxx/cpu_init.c b/cpu/mpc5xxx/cpu_init.c
index 4a370ff..d744030 100644 (file)
--- a/cpu/mpc5xxx/cpu_init.c
+++ b/cpu/mpc5xxx/cpu_init.c
@@ -123,7 +123,7 @@ void cpu_init_f (void)
 #endif
 
 #if defined(CFG_CS7_START) && defined(CFG_CS7_SIZE)
-       *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS5_START);
+       *(vu_long *)MPC5XXX_CS7_START = START_REG(CFG_CS7_START);
        *(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CFG_CS7_START, CFG_CS7_SIZE);
        addecr |= (1 << 27);
 #endif
@@ -152,21 +152,25 @@ void cpu_init_f (void)
        /* enable timebase */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13);
 
-# if defined(CFG_IPBSPEED_133)
+       /* Enable snooping for RAM */
+       *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
+       *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
+
+# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
        /* Motorola reports IPB should better run at 133 MHz. */
        *(vu_long *)MPC5XXX_ADDECR |= 1;
        /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
        addecr = *(vu_long *)MPC5XXX_CDM_CFG;
        addecr &= ~0x103;
-#  if defined(CFG_PCISPEED_66)
+#  if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
        /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
        addecr |= 0x01;
 #  else
        /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
        addecr |= 0x02;
-#  endif /* CFG_PCISPEED_66 */
+#  endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
        *(vu_long *)MPC5XXX_CDM_CFG = addecr;
-# endif        /* CFG_IPBSPEED_133 */
+# endif        /* CFG_IPBCLK_EQUALS_XLBCLK */
        /* Configure the XLB Arbiter */
        *(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
        *(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;