#include <mpc83xx.h>
#include <i2c.h>
#include <miiphy.h>
+#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/processor.h>
static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
-const qe_iop_conf_t qe_iop_conf_tab[] = {
- /* port pin dir open_drain assign */
-#if defined(CONFIG_ARCH_MPC8360)
- /* MDIO */
- {0, 1, 3, 0, 2}, /* MDIO */
- {0, 2, 1, 0, 1}, /* MDC */
-
- /* UCC4 - UEC */
- {1, 14, 1, 0, 1}, /* TxD0 */
- {1, 15, 1, 0, 1}, /* TxD1 */
- {1, 20, 2, 0, 1}, /* RxD0 */
- {1, 21, 2, 0, 1}, /* RxD1 */
- {1, 18, 1, 0, 1}, /* TX_EN */
- {1, 26, 2, 0, 1}, /* RX_DV */
- {1, 27, 2, 0, 1}, /* RX_ER */
- {1, 24, 2, 0, 1}, /* COL */
- {1, 25, 2, 0, 1}, /* CRS */
- {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
- {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
-
- /* DUART - UART2 */
- {5, 0, 1, 0, 2}, /* UART2_SOUT */
- {5, 2, 1, 0, 1}, /* UART2_RTS */
- {5, 3, 2, 0, 2}, /* UART2_SIN */
- {5, 1, 2, 0, 3}, /* UART2_CTS */
-#elif !defined(CONFIG_ARCH_MPC8309)
- /* Local Bus */
- {0, 16, 1, 0, 3}, /* LA00 */
- {0, 17, 1, 0, 3}, /* LA01 */
- {0, 18, 1, 0, 3}, /* LA02 */
- {0, 19, 1, 0, 3}, /* LA03 */
- {0, 20, 1, 0, 3}, /* LA04 */
- {0, 21, 1, 0, 3}, /* LA05 */
- {0, 22, 1, 0, 3}, /* LA06 */
- {0, 23, 1, 0, 3}, /* LA07 */
- {0, 24, 1, 0, 3}, /* LA08 */
- {0, 25, 1, 0, 3}, /* LA09 */
- {0, 26, 1, 0, 3}, /* LA10 */
- {0, 27, 1, 0, 3}, /* LA11 */
- {0, 28, 1, 0, 3}, /* LA12 */
- {0, 29, 1, 0, 3}, /* LA13 */
- {0, 30, 1, 0, 3}, /* LA14 */
- {0, 31, 1, 0, 3}, /* LA15 */
-
- /* MDIO */
- {3, 4, 3, 0, 2}, /* MDIO */
- {3, 5, 1, 0, 2}, /* MDC */
-
- /* UCC4 - UEC */
- {1, 18, 1, 0, 1}, /* TxD0 */
- {1, 19, 1, 0, 1}, /* TxD1 */
- {1, 22, 2, 0, 1}, /* RxD0 */
- {1, 23, 2, 0, 1}, /* RxD1 */
- {1, 26, 2, 0, 1}, /* RxER */
- {1, 28, 2, 0, 1}, /* Rx_DV */
- {1, 30, 1, 0, 1}, /* TxEN */
- {1, 31, 2, 0, 1}, /* CRS */
- {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
-#endif
-
- /* END of table */
- {0, 0, 0, 0, QE_IOP_TAB_END},
-};
-
static int piggy_present(void)
{
struct km_bec_fpga __iomem *base =
int last_stage_init(void)
{
#if defined(CONFIG_TARGET_KMCOGE5NE)
- struct bfticu_iomap *base =
- (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
+ /*
+ * BFTIC3 on the local bus CS4
+ */
+ struct bfticu_iomap *base = (struct bfticu_iomap *)0xB0000000;
u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
if (dip_switch != 0) {
udelay(200);
setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
- msize = CONFIG_SYS_DDR_SIZE << 20;
disable_addr_trans();
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
+ msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
enable_addr_trans();
msize /= (1024 * 1024);
- if (CONFIG_SYS_DDR_SIZE != msize) {
+ if (CONFIG_SYS_SDRAM_SIZE >> 20 != msize) {
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size >> 1, ddr_size_log2++)
int checkboard(void)
{
- puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
+ puts("Board: Hitachi " CONFIG_SYS_CONFIG_NAME);
if (piggy_present())
puts(" with PIGGY.");
return 0;
}
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
- /*
- * These match CONFIG_SYS_MEMTEST_START and
- * (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START)
- */
- *vstart = 0x00100000;
- *size = 0xe00000;
+ *vstart = CONFIG_SYS_MEMTEST_START;
+ *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
return 0;