Merge branch '2022-08-04-Kconfig-migrations'

[platform/kernel/u-boot.git] / board / imgtec / malta / lowlevel_init.S

diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
index ae09c27..bed2497 100644 (file)
--- a/board/imgtec/malta/lowlevel_init.S
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #include <config.h>
@@ -10,6 +9,7 @@
 #include <pci.h>
 
 #include <asm/addrspace.h>
+#include <asm/asm.h>
 #include <asm/regdef.h>
 #include <asm/malta.h>
 #include <asm/mipsregs.h>
@@ -24,18 +24,11 @@
 
        .text
        .set noreorder
-       .set mips32
 
        .globl  lowlevel_init
 lowlevel_init:
-       /* disable any L2 cache for now */
-       sync
-       mfc0    t0, CP0_CONFIG, 2
-       ori     t0, t0, 0x1 << 12
-       mtc0    t0, CP0_CONFIG, 2
-
        /* detect the core card */
-       li      t0, KSEG1ADDR(MALTA_REVISION)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_REVISION)
        lw      t0, 0(t0)
        srl     t0, t0, MALTA_REVISION_CORID_SHF
        andi    t0, t0, (MALTA_REVISION_CORID_MSK >> \
@@ -69,12 +62,12 @@ lowlevel_init:
         */
 _gt64120:
        /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-       li      t1, KSEG1ADDR(GT_DEF_BASE)
+       PTR_LI  t1, CKSEG1ADDR(GT_DEF_BASE)
        li      t0, CPU_TO_GT32(0xdf000000)
        sw      t0, GT_ISD_OFS(t1)
 
        /* setup MEM-to-PCI0 mapping */
-       li      t1, KSEG1ADDR(MALTA_GT_BASE)
+       PTR_LI  t1, CKSEG1ADDR(MALTA_GT_BASE)
 
        /* setup PCI0 io window to 0x18000000-0x181fffff */
        li      t0, CPU_TO_GT32(0xc0000000)
@@ -101,7 +94,7 @@ _gt64120:
         */
 _msc01:
        /* setup peripheral bus controller clock divide */
-       li      t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
        li      t1, 0x1 << MSC01_PBC_CLKCFG_SHF
        sw      t1, MSC01_PBC_CLKCFG_OFS(t0)
 
@@ -123,9 +116,9 @@ _msc01:
        sw      t1, MSC01_PBC_CS0CFG_OFS(t0)
 
        /* setup basic address decode */
-       li      t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
        li      t1, 0x0
-       li      t2, -CONFIG_SYS_MEM_SIZE
+       li      t2, -CONFIG_SYS_SDRAM_SIZE
        sw      t1, MSC01_BIU_MCBAS1L_OFS(t0)
        sw      t2, MSC01_BIU_MCMSK1L_OFS(t0)
        sw      t1, MSC01_BIU_MCBAS2L_OFS(t0)
@@ -158,7 +151,7 @@ _msc01:
        sw      t2, MSC01_BIU_IP3MSK2L_OFS(t0)
 
        /* setup PCI memory */
-       li      t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+       PTR_LI  t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
        li      t1, MALTA_MSC01_PCIMEM_BASE
        li      t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
        li      t3, MALTA_MSC01_PCIMEM_MAP
@@ -175,7 +168,7 @@ _msc01:
        sw      t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
 
        /* setup PCI_BAR0 memory window */
-       li      t1, -CONFIG_SYS_MEM_SIZE
+       li      t1, -CONFIG_SYS_SDRAM_SIZE
        sw      t1, MSC01_PCI_BAR0_OFS(t0)
 
        /* setup PCI to SysCon/CPU translation */