+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007-2008
* Stelian Pop <stelian@popies.net>
* Lead Tech Design <www.leadtechdesign.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <asm/sizes.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <net.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <linux/sizes.h>
#include <asm/arch/at91sam9263.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
#include <atmel_lcdc.h>
-#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
-#include <net.h>
-#endif
-#include <netdev.h>
+#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long csa;
at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
/* Enable CS3 */
csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
AT91_SMC_MODE_TDF_CYCLE(2),
&smc->cs[3].mode);
- writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE,
- &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOCDE);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
}
#endif
-#ifdef CONFIG_MACB
-static void at91sam9263ek_macb_hw_init(void)
-{
- unsigned long erstl;
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
- at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
- at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
- /* Enable clock */
- writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
-
- /*
- * Disable pull-up on:
- * RXDV (PC25) => PHY normal mode (not Test mode)
- * ERX0 (PE25) => PHY ADDR0
- * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
- *
- * PHY has internal pull-down
- */
-
- writel(1 << 25, &pio->pioc.pudr);
- writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
-
- erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
- /* Need to reset PHY -> 500ms reset */
- writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
- AT91_RSTC_MR_URSTEN, &rstc->mr);
-
- writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
- /* Wait for end hardware reset */
- while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
- ;
-
- /* Restore NRST value */
- writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
-
- /* Re-enable pull-up */
- writel(1 << 25, &pio->pioc.puer);
- writel((1 << 25) | (1 <<26), &pio->pioe.puer);
-
- at91_macb_hw_init();
-}
-#endif
-
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_clk: 4965000,
- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 5,
- vl_left_margin: 1,
- vl_right_margin:33,
- vl_vsync_len: 1,
- vl_upper_margin:1,
- vl_lower_margin:0,
- mmio: ATMEL_BASE_LCDC,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
static void at91sam9263ek_lcd_hw_init(void)
{
- at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-
at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
- writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
+ at91_periph_clk_enable(ATMEL_ID_LCDC);
gd->fb_base = ATMEL_BASE_SRAM0;
}
#include <nand.h>
#include <version.h>
-#ifndef CONFIG_SYS_NO_FLASH
-extern flash_info_t flash_info[];
+#ifdef CONFIG_MTD_NOR_FLASH
+#include <flash.h>
#endif
void lcd_show_board_info(void)
{
ulong dram_size, nand_size;
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
ulong flash_size;
#endif
int i;
dram_size += gd->bd->bi_dram[i].size;
nand_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
- nand_size += nand_info[i].size;
-#ifndef CONFIG_SYS_NO_FLASH
+ nand_size += get_nand_dev_by_index(i)->size;
+#ifdef CONFIG_MTD_NOR_FLASH
flash_size = 0;
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
flash_size += flash_info[i].size;
lcd_printf (" %ld MB SDRAM, %ld MB NAND",
dram_size >> 20,
nand_size >> 20 );
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
lcd_printf (",\n %ld MB NOR",
flash_size >> 20);
#endif
#endif /* CONFIG_LCD_INFO */
#endif
-int board_early_init_f(void)
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
- /* Enable clocks for all PIOs */
- writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
- (1 << ATMEL_ID_PIOCDE),
- &pmc->pcer);
-
at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
return 0;
}
+#endif
int board_init(void)
{
#ifdef CONFIG_CMD_NAND
at91sam9263ek_nand_hw_init();
#endif
-#ifdef CONFIG_HAS_DATAFLASH
- at91_set_pio_output(AT91_PIO_PORTE, 20, 1); /* select spi0 clock */
- at91_spi0_hw_init(1 << 0);
-#endif
-#ifdef CONFIG_MACB
- at91sam9263ek_macb_hw_init();
-#endif
#ifdef CONFIG_USB_OHCI_NEW
at91_uhp_hw_init();
#endif
{
}
#endif
-
-int board_eth_init(bd_t *bis)
-{
- int rc = 0;
-#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x00);
-#endif
- return rc;
-}