Merge branch '2022-08-04-Kconfig-migrations'

[platform/kernel/u-boot.git] / arch / powerpc / include / asm / config_mpc85xx.h

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index a43e6e5..458c0a8 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -16,9 +16,6 @@
 
 #include <fsl_ddrc_version.h>
 
-/* IP endianness */
-#define CONFIG_SYS_FSL_IFC_BE
-
 #if defined(CONFIG_ARCH_MPC8548)
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS  1
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
@@ -74,7 +71,6 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM       2
 
 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -91,7 +87,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P3041)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -108,7 +103,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     4
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_NUM_FM1_DTSEC       4
@@ -126,7 +120,6 @@
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
 
 #elif defined(CONFIG_ARCH_P5040)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     3
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_NUM_FM1_DTSEC       5
@@ -160,8 +153,6 @@
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
 
 #elif defined(CONFIG_ARCH_T4240)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #ifdef CONFIG_ARCH_T4240
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 4 }
@@ -183,7 +174,6 @@
 #define CONFIG_SYS_NUM_FMAN            2
 #define CONFIG_SYS_PME_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM1_CLK             3
 #define CONFIG_SYS_FM2_CLK             3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
@@ -197,7 +187,6 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_SRDS_1
 #define CONFIG_SYS_FSL_SRDS_2
@@ -205,14 +194,12 @@
 #define CONFIG_SYS_NUM_FMAN            1
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  4
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x60000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.4"
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
 
 #ifdef CONFIG_ARCH_B4860
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_MAX_DSP_CPUS            12
 #define CONFIG_NUM_DSP_CPUS            6
 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS   2
@@ -226,15 +213,12 @@
 #else
 #define CONFIG_MAX_DSP_CPUS            2
 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS   1
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 4 }
 #define CONFIG_SYS_NUM_FM1_DTSEC       4
 #define CONFIG_SYS_NUM_FM1_10GEC       0
 #endif
 
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3         /* QMAN version 3 */
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
@@ -244,7 +228,6 @@
 #define CONFIG_PME_PLAT_CLK_DIV                2
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK             CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE       0x30000
@@ -259,10 +242,7 @@
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_FSL_CORENET          /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3  /* QMAN version 3 */
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FSL_NUM_CC_PLL      2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
@@ -285,8 +265,6 @@
 #define QE_NUM_OF_SNUM                 28
 
 #elif defined(CONFIG_ARCH_T2080)
-#define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */
-#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS     2
 #define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN            1
@@ -305,7 +283,6 @@
 #define CONFIG_SYS_PME_CLK             CONFIG_PME_PLAT_CLK_DIV
 #define CONFIG_SYS_FM1_CLK             0
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
-#define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_FM_MURAM_SIZE       0x28000
 #define CONFIG_SYS_FSL_TBCLK_DIV       16
 #define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v3.0"