ARM: Add workaround for I-Cache line size mismatch between CPU cores

[platform/kernel/linux-exynos.git] / arch / arm / mm / cache-v7.S

diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 50a70ed..69cfee6 100644 (file)
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,14 @@
 
 #include "proc-macros.S"
 
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif
 /*
  * The secondary kernel init calls v7_flush_dcache_all before it enables
  * the L1; however, the L1 comes out of reset in an undefined state, so
@@ -283,7 +291,12 @@ ENTRY(v7_coherent_user_range)
        cmp     r12, r1
        blo     1b
        dsb     ishst
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+       ldr     r3, =icache_size
+       ldr     r2, [r3, #0]
+#else
        icache_line_size r2, r3
+#endif
        sub     r3, r2, #1
        bic     r12, r0, r3
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