-#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
-
-#define CFG_FLASH0 0xFE000000
-#define CFG_FLASH1 0xFC000000
-#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
-
-#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
-#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
-
-#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
-#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
-#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
-#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
-
-#define CFG_FLASH_CFI /* flash is CFI compat. */
-#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
-
-#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
-#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
-#undef CFG_FLASH_CHECKSUM
-#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-
-#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-
-#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
-#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
-
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+
+#define CONFIG_SYS_FLASH0 0xFE000000
+#define CONFIG_SYS_FLASH1 0xFC000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
+
+#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
+#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
+
+#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
+#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
+
+#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
+#undef CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
+#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
+
+#define CONFIG_SYS_INIT_RAM_LOCK 1
+#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data*/
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
+
+/* FPGA and NAND */
+#define CONFIG_SYS_FPGA_BASE 0xc0000000
+#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
+#define CONFIG_SYS_HMI_BASE 0xc0010000
+#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
+#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
+
+#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_CMD_NAND
+
+/* LIME GDC */
+#define CONFIG_SYS_LIME_BASE 0xc8000000
+#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
+#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
+
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_MB862xx
+#define CONFIG_VIDEO_MB862xx_ACCEL
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define VIDEO_FB_16BPP_PIXEL_SWAP
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
+
+/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
+#define CONFIG_SYS_MB862xx_CCF 0x10000
+/* SDRAM parameter */
+#define CONFIG_SYS_MB862xx_MMR 0x4157BA63