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Fix problems with SNTP support;
[platform/kernel/u-boot.git]
/
include
/
configs
/
PM826.h
diff --git
a/include/configs/PM826.h
b/include/configs/PM826.h
index
b56da69
..
a4c4fc9
100644
(file)
--- a/
include/configs/PM826.h
+++ b/
include/configs/PM826.h
@@
-1,5
+1,5
@@
/*
/*
- * (C) Copyright 2001
+ * (C) Copyright 2001
-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@
-40,8
+40,6
@@
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
@@
-155,12
+153,28
@@
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_DATE | \
- CFG_CMD_EEPROM | \
- CFG_CMD_I2C | \
- CFG_CMD_DOC)
+#ifdef CONFIG_PCI
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DOC | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PCI | \
+ CFG_CMD_SNTP )
+#else /* ! PCI */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DOC | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NFS | \
+ CFG_CMD_SNTP )
+#endif /* CONFIG_PCI */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@@
-198,7
+212,7
@@
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-#define CFG_RESET_ADDRESS 0xF
F
FFFFFC /* "bad" address */
+#define CFG_RESET_ADDRESS 0xF
D
FFFFFC /* "bad" address */
/*
* For booting Linux, the board info and command line data
/*
* For booting Linux, the board info and command line data
@@
-210,15
+224,18
@@
/*-----------------------------------------------------------------------
* Flash and Boot ROM mapping
*/
/*-----------------------------------------------------------------------
* Flash and Boot ROM mapping
*/
-
-#define CFG_BOOTROM_BASE 0x60000000
-#define CFG_BOOTROM_SIZE 0x00080000
+#ifdef CONFIG_FLASH_32MB
#define CFG_FLASH0_BASE 0x40000000
#define CFG_FLASH0_SIZE 0x02000000
#define CFG_FLASH0_BASE 0x40000000
#define CFG_FLASH0_SIZE 0x02000000
-#define CFG_DOC_BASE 0x60000000
+#else
+#define CFG_FLASH0_BASE 0xFF000000
+#define CFG_FLASH0_SIZE 0x00800000
+#endif
+#define CFG_BOOTROM_BASE 0xFF800000
+#define CFG_BOOTROM_SIZE 0x00080000
+#define CFG_DOC_BASE 0xFF800000
#define CFG_DOC_SIZE 0x00100000
#define CFG_DOC_SIZE 0x00100000
-
/* Flash bank size (for preliminary settings)
*/
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
/* Flash bank size (for preliminary settings)
*/
#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
@@
-227,8
+244,11
@@
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
+#ifdef CONFIG_FLASH_32MB
+#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
+#else
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
-
+#endif
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
@@
-245,8
+265,8
@@
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_ENV_OFFSET
0
-#define CFG_ENV_SIZE
2048
+#define CFG_ENV_OFFSET
512
+#define CFG_ENV_SIZE
(2048 - 512)
#endif
/*-----------------------------------------------------------------------
#endif
/*-----------------------------------------------------------------------
@@
-303,6
+323,12
@@
# define CFG_RAMBOOT
#endif
# define CFG_RAMBOOT
#endif
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_EEPRO100
+#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
+#endif
+
/*
* Internal Definitions
*
/*
* Internal Definitions
*
@@
-331,7
+357,7
@@
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-
HID0_IFEM|HID0_ABE)
+ HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
@@
-369,10
+395,10
@@
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
#else
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-
SYPCR_SWRI|SYPCR_SWP)
+ SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
@@
-395,7
+421,7
@@
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
* SCCR - System Clock Control 9-8
*-----------------------------------------------------------------------
*/
-#define CFG_SCCR (SCCR_DFBRG0
1
)
+#define CFG_SCCR (SCCR_DFBRG0
0
)
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
/*-----------------------------------------------------------------------
* RCCR - RISC Controller Configuration 13-7
@@
-410,7
+436,6
@@
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH
* 1 60x SDRAM 64 bit SDRAM
* ---- --- ------- ------ ------
* 0 60x GPCM 64 bit FLASH
* 1 60x SDRAM 64 bit SDRAM
- * 2 Local SDRAM 32 bit SDRAM
*
*/
*
*/
@@
-424,7
+449,12
@@
*/
#define CFG_MIN_AM_MASK 0xC0000000
*/
#define CFG_MIN_AM_MASK 0xC0000000
-#define CFG_MPTPR 0x1F00
+/*
+ * we use the same values for 32 MB and 128 MB SDRAM
+ * refresh rate = 7.73 uS (64 MHz Bus Clock)
+ */
+#define CFG_MPTPR 0x2000
+#define CFG_PSRT 0x0E
#define CFG_MRS_OFFS 0x00000000
#define CFG_MRS_OFFS 0x00000000
@@
-466,16
+496,16
@@
* Bank 0 - Flash (64 bit wide)
*/
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
* Bank 0 - Flash (64 bit wide)
*/
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
-
BRx_PS_64 |\
-
BRx_MS_GPCM_P |\
-
BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
-
ORxG_CSNT |\
-
ORxG_ACS_DIV1 |\
-
ORxG_SCY_3_CLK |\
-
ORxG_EHTR |\
-
ORxG_TRLX)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxG_EHTR |\
+ ORxG_TRLX)
/*
* Bank 1 - Disk-On-Chip
/*
* Bank 1 - Disk-On-Chip
@@
-496,46
+526,46
@@
/* Bank 2 - SDRAM
*/
/* Bank 2 - SDRAM
*/
-#define CFG_PSRT 0x0F
+
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
-
BRx_PS_64 |\
-
BRx_MS_SDRAM_P |\
-
BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
/* SDRAM initialization values for 8-column chips
*/
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
/* SDRAM initialization values for 8-column chips
*/
#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
-
ORxS_BPD_4 |\
-
ORxS_ROWST_PBI0_A9 |\
-
ORxS_NUMR_12)
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A9 |\
+ ORxS_NUMR_12)
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
-
PSDMR_BSMA_A14_A16 |\
-
PSDMR_SDA10_PBI0_A10 |\
-
PSDMR_RFRC_7_CLK |\
-
PSDMR_PRETOACT_2W |\
-
PSDMR_ACTTORW_1W |\
-
PSDMR_LDOTOPRE_1C |\
-
PSDMR_WRC_1C |\
-
PSDMR_CL_2)
+ PSDMR_BSMA_A14_A16 |\
+ PSDMR_SDA10_PBI0_A10 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_1W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
/* SDRAM initialization values for 9-column chips
*/
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
/* SDRAM initialization values for 9-column chips
*/
#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
-
ORxS_BPD_4 |\
-
ORxS_ROWST_PBI0_A7 |\
-
ORxS_NUMR_13)
+ ORxS_BPD_4 |\
+ ORxS_ROWST_PBI0_A7 |\
+ ORxS_NUMR_13)
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
-
PSDMR_BSMA_A13_A15 |\
-
PSDMR_SDA10_PBI0_A9 |\
-
PSDMR_RFRC_7_CLK |\
-
PSDMR_PRETOACT_2W |\
-
PSDMR_ACTTORW_1W |\
-
PSDMR_LDOTOPRE_1C |\
-
PSDMR_WRC_1C |\
-
PSDMR_CL_2)
+ PSDMR_BSMA_A13_A15 |\
+ PSDMR_SDA10_PBI0_A9 |\
+ PSDMR_RFRC_7_CLK |\
+ PSDMR_PRETOACT_2W |\
+ PSDMR_ACTTORW_1W |\
+ PSDMR_LDOTOPRE_1C |\
+ PSDMR_WRC_1C |\
+ PSDMR_CL_2)
#define CFG_OR2_PRELIM CFG_OR2_9COL
#define CFG_PSDMR CFG_PSDMR_9COL
#define CFG_OR2_PRELIM CFG_OR2_9COL
#define CFG_PSDMR CFG_PSDMR_9COL