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Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE
[platform/kernel/u-boot.git]
/
include
/
configs
/
ATUM8548.h
diff --git
a/include/configs/ATUM8548.h
b/include/configs/ATUM8548.h
index
7ee05e5
..
388234c
100644
(file)
--- a/
include/configs/ATUM8548.h
+++ b/
include/configs/ATUM8548.h
@@
-67,7
+67,6
@@
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
/*
* Only possible on E500 Version 2 or newer cores.
@@
-92,9
+91,6
@@
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
/* DDR Setup */
#define CONFIG_FSL_DDR2
/* DDR Setup */
#define CONFIG_FSL_DDR2
@@
-177,7
+173,7
@@
#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE
TEXT_BASE
/* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE
CONFIG_SYS_TEXT_BASE
/* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI 1
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI 1
@@
-204,7
+200,6
@@
/* Serial Port */
#define CONFIG_CONS_INDEX 1
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
@@
-244,27
+239,27
@@
*/
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
*/
#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_B
ASE
0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_B
ASE
+#define CONFIG_SYS_PCI1_MEM_B
US
0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_B
US
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI1_IO_B
ASE
0x00000000
+#define CONFIG_SYS_PCI1_IO_B
US
0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_B
ASE
0xC0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_B
ASE
+#define CONFIG_SYS_PCI2_MEM_B
US
0xC0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_B
US
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_B
ASE
0x00000000
+#define CONFIG_SYS_PCI2_IO_B
US
0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
#ifdef CONFIG_PCIE1
#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_B
ASE
0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_B
ASE
+#define CONFIG_SYS_PCIE1_MEM_B
US
0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_B
US
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_B
ASE
0x00000000
+#define CONFIG_SYS_PCIE1_IO_B
US
0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif