-#else
- /*
- * Manually set up DDR parameters
- */
- #define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
- #define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
- #define CFG_DDR_CS0_CONFIG 0x80000102
- #define CFG_DDR_TIMING_0 0x00260802
- #define CFG_DDR_TIMING_1 0x38355322
- #define CFG_DDR_TIMING_2 0x039048c7
- #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
- #define CFG_DDR_MODE 0x00000432
- #define CFG_DDR_INTERVAL 0x05150100
- #define DDR_SDRAM_CFG 0x43000000
-#endif
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_VERY_BIG_RAM
+
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL 2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
+
+/* Manually set up DDR parameters */
+#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
+#define CONFIG_SYS_DDR_TIMING_0 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1 0x38355322
+#define CONFIG_SYS_DDR_TIMING_2 0x039048c7
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_MODE 0x00000432
+#define CONFIG_SYS_DDR_INTERVAL 0x05150100
+#define DDR_SDRAM_CFG 0x43000000