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ARM: Add workaround for I-Cache line size mismatch between CPU cores
[platform/kernel/linux-exynos.git]
/
arch
/
arm
/
include
/
asm
/
cacheflush.h
diff --git
a/arch/arm/include/asm/cacheflush.h
b/arch/arm/include/asm/cacheflush.h
index
74504b1
..
060edfc
100644
(file)
--- a/
arch/arm/include/asm/cacheflush.h
+++ b/
arch/arm/include/asm/cacheflush.h
@@
-481,4
+481,11
@@
static inline void __sync_cache_range_r(volatile void *p, size_t size)
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
void *kaddr, unsigned long len);
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
void *kaddr, unsigned long len);
+
+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+void check_cpu_icache_size(int cpuid);
+#else
+static inline void check_cpu_icache_size(int cpuid) { }
+#endif
+
#endif
#endif