src/i965_post_processing.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #ifndef __I965_POST_PROCESSING_H__
  30 #define __I965_POST_PROCESSING_H__
  31
  32 #define MAX_PP_SURFACES 48
  33
  34 #define I965_PP_FLAG_TOP_FIELD          1
  35 #define I965_PP_FLAG_BOTTOM_FIELD       2
  36 #define I965_PP_FLAG_MCDI               4
  37 #define I965_PP_FLAG_AVS                8
  38
  39 enum
  40 {
  41     PP_NULL = 0,
  42     PP_NV12_LOAD_SAVE_N12,
  43     PP_NV12_LOAD_SAVE_PL3,
  44     PP_PL3_LOAD_SAVE_N12,
  45     PP_PL3_LOAD_SAVE_PL3,
  46     PP_NV12_SCALING,
  47     PP_NV12_AVS,
  48     PP_NV12_DNDI,
  49     PP_NV12_DN,
  50     PP_NV12_LOAD_SAVE_PA,
  51     PP_PL3_LOAD_SAVE_PA,
  52 };
  53
  54 #define NUM_PP_MODULES                  11
  55
  56 struct i965_post_processing_context;
  57
  58 struct pp_load_save_context
  59 {
  60     int dest_w;
  61     int dest_h;
  62 };
  63
  64 struct pp_scaling_context
  65 {
  66     int dest_x; /* in pixel */
  67     int dest_y; /* in pixel */
  68     int dest_w;
  69     int dest_h;
  70     float src_normalized_x;
  71     float src_normalized_y;
  72 };
  73
  74 struct pp_avs_context
  75 {
  76     int dest_x; /* in pixel */
  77     int dest_y; /* in pixel */
  78     int dest_w;
  79     int dest_h;
  80     float src_normalized_x;
  81     float src_normalized_y;
  82     int src_w;
  83     int src_h;
  84 };
  85
  86 struct pp_dndi_context
  87 {
  88     int dest_w;
  89     int dest_h;
  90 };
  91
  92 struct pp_dn_context
  93 {
  94     int dest_w;
  95     int dest_h;
  96 };
  97
  98 struct pp_module
  99 {
 100     struct i965_kernel kernel;
 101
 102     /* others */
 103     VAStatus (*initialize)(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
 104                            const struct i965_surface *src_surface,
 105                            const VARectangle *src_rect,
 106                            struct i965_surface *dst_surface,
 107                            const VARectangle *dst_rect,
 108                            void *filter_param);
 109 };
 110
 111 struct pp_static_parameter
 112 {
 113     struct {
 114         /* Procamp r1.0 */
 115         float procamp_constant_c0;
 116
 117         /* Load and Same r1.1 */
 118         unsigned int source_packed_y_offset:8;
 119         unsigned int source_packed_u_offset:8;
 120         unsigned int source_packed_v_offset:8;
 121         unsigned int pad0:8;
 122
 123         union {
 124             /* Load and Save r1.2 */
 125             struct {
 126                 unsigned int destination_packed_y_offset:8;
 127                 unsigned int destination_packed_u_offset:8;
 128                 unsigned int destination_packed_v_offset:8;
 129                 unsigned int pad0:8;
 130             } load_and_save;
 131
 132             /* CSC r1.2 */
 133             struct {
 134                 unsigned int destination_rgb_format:8;
 135                 unsigned int pad0:24;
 136             } csc;
 137         } r1_2;
 138
 139         /* Procamp r1.3 */
 140         float procamp_constant_c1;
 141
 142         /* Procamp r1.4 */
 143         float procamp_constant_c2;
 144
 145         /* DI r1.5 */
 146         unsigned int statistics_surface_picth:16;  /* Devided by 2 */
 147         unsigned int pad1:16;
 148
 149         union {
 150             /* DI r1.6 */
 151             struct {
 152                 unsigned int pad0:24;
 153                 unsigned int top_field_first:8;
 154             } di;
 155
 156             /* AVS/Scaling r1.6 */
 157             float normalized_video_y_scaling_step;
 158         } r1_6;
 159
 160         /* Procamp r1.7 */
 161         float procamp_constant_c5;
 162     } grf1;
 163
 164     struct {
 165         /* Procamp r2.0 */
 166         float procamp_constant_c3;
 167
 168         /* MBZ r2.1*/
 169         unsigned int pad0;
 170
 171         /* WG+CSC r2.2 */
 172         float wg_csc_constant_c4;
 173
 174         /* WG+CSC r2.3 */
 175         float wg_csc_constant_c8;
 176
 177         /* Procamp r2.4 */
 178         float procamp_constant_c4;
 179
 180         /* MBZ r2.5 */
 181         unsigned int pad1;
 182
 183         /* MBZ r2.6 */
 184         unsigned int pad2;
 185
 186         /* WG+CSC r2.7 */
 187         float wg_csc_constant_c9;
 188     } grf2;
 189
 190     struct {
 191         /* WG+CSC r3.0 */
 192         float wg_csc_constant_c0;
 193
 194         /* Blending r3.1 */
 195         float scaling_step_ratio;
 196
 197         /* Blending r3.2 */
 198         float normalized_alpha_y_scaling;
 199
 200         /* WG+CSC r3.3 */
 201         float wg_csc_constant_c4;
 202
 203         /* WG+CSC r3.4 */
 204         float wg_csc_constant_c1;
 205
 206         /* ALL r3.5 */
 207         int horizontal_origin_offset:16;
 208         int vertical_origin_offset:16;
 209
 210         /* Shared r3.6*/
 211         union {
 212             /* Color filll */
 213             unsigned int color_pixel;
 214
 215             /* WG+CSC */
 216             float wg_csc_constant_c2;
 217         } r3_6;
 218
 219         /* WG+CSC r3.7 */
 220         float wg_csc_constant_c3;
 221     } grf3;
 222
 223     struct {
 224         /* WG+CSC r4.0 */
 225         float wg_csc_constant_c6;
 226
 227         /* ALL r4.1 MBZ ???*/
 228         unsigned int pad0;
 229
 230         /* Shared r4.2 */
 231         union {
 232             /* AVS */
 233             struct {
 234                 unsigned int pad1:15;
 235                 unsigned int nlas:1;
 236                 unsigned int pad2:16;
 237             } avs;
 238
 239             /* DI */
 240             struct {
 241                 unsigned int motion_history_coefficient_m2:8;
 242                 unsigned int motion_history_coefficient_m1:8;
 243                 unsigned int pad0:16;
 244             } di;
 245         } r4_2;
 246
 247         /* WG+CSC r4.3 */
 248         float wg_csc_constant_c7;
 249
 250         /* WG+CSC r4.4 */
 251         float wg_csc_constant_c10;
 252
 253         /* AVS r4.5 */
 254         float source_video_frame_normalized_horizontal_origin;
 255
 256         /* MBZ r4.6 */
 257         unsigned int pad1;
 258
 259         /* WG+CSC r4.7 */
 260         float wg_csc_constant_c11;
 261     } grf4;
 262 };
 263
 264 struct pp_inline_parameter
 265 {
 266     struct {
 267         /* ALL r5.0 */
 268         int destination_block_horizontal_origin:16;
 269         int destination_block_vertical_origin:16;
 270
 271         /* Shared r5.1 */
 272         union {
 273             /* AVS/Scaling */
 274             float source_surface_block_normalized_horizontal_origin;
 275
 276             /* FMD */
 277             struct {
 278                 unsigned int variance_surface_vertical_origin:16;
 279                 unsigned int pad0:16;
 280             } fmd;
 281         } r5_1;
 282
 283         /* AVS/Scaling r5.2 */
 284         float source_surface_block_normalized_vertical_origin;
 285
 286         /* Alpha r5.3 */
 287         float alpha_surface_block_normalized_horizontal_origin;
 288
 289         /* Alpha r5.4 */
 290         float alpha_surface_block_normalized_vertical_origin;
 291
 292         /* Alpha r5.5 */
 293         unsigned int alpha_mask_x:16;
 294         unsigned int alpha_mask_y:8;
 295         unsigned int block_count_x:8;
 296
 297         /* r5.6 */
 298         unsigned int block_horizontal_mask:16;
 299         unsigned int block_vertical_mask:8;
 300         unsigned int number_blocks:8;
 301
 302         /* AVS/Scaling r5.7 */
 303         float normalized_video_x_scaling_step;
 304     } grf5;
 305
 306     struct {
 307         /* AVS r6.0 */
 308         float video_step_delta;
 309
 310         /* r6.1-r6.7 */
 311         unsigned int padx[7];
 312     } grf6;
 313 };
 314
 315 struct gen7_pp_static_parameter
 316 {
 317     struct {
 318         /* r1.0-r1.5 */
 319         unsigned int padx[6];
 320         /* r1.6 */
 321         unsigned int di_statistics_surface_pitch_div2:16;
 322         unsigned int di_statistics_surface_height_div4:16;
 323         /* r1.7 */
 324         unsigned int di_top_field_first:8;
 325         unsigned int pad0:16;
 326         unsigned int pointer_to_inline_parameter:8; /* value: 7 */
 327     } grf1;
 328
 329     struct {
 330         /* r2.0-r2.6 */
 331         unsigned int padx[7];
 332         /* r2.7 */
 333         unsigned int di_destination_packed_y_component_offset:8;
 334         unsigned int di_destination_packed_u_component_offset:8;
 335         unsigned int di_destination_packed_v_component_offset:8;
 336         unsigned int pad0:8;
 337     } grf2;
 338
 339     struct {
 340         float sampler_load_horizontal_scaling_step_ratio;
 341         unsigned int padx[7];
 342     } grf3;
 343
 344     struct {
 345         float sampler_load_vertical_scaling_step;
 346         unsigned int pad0;
 347         unsigned int di_hoffset_svf_from_dvf:16;
 348         unsigned int di_voffset_svf_from_dvf:16;
 349         unsigned int padx[5];
 350     } grf4;
 351
 352     struct {
 353         float sampler_load_vertical_frame_origin;
 354         unsigned int padx[7];
 355     } grf5;
 356
 357     struct {
 358         float sampler_load_horizontal_frame_origin;
 359         unsigned int padx[7];
 360     } grf6;
 361 };
 362
 363 struct gen7_pp_inline_parameter
 364 {
 365     struct {
 366         /* r7.0 */
 367         unsigned int destination_block_horizontal_origin:16;
 368         unsigned int destination_block_vertical_origin:16;
 369         /* r7.1: 0xffffffff */
 370         unsigned int constant_0;
 371         /* r7.2 */
 372         unsigned int pad0;
 373         /* r7.3 */
 374         unsigned int pad1;
 375         /* r7.4 */
 376         float sampler_load_main_video_x_scaling_step;
 377         /* r7.5 */
 378         unsigned int pad2;
 379         /* r7.6: must be zero */
 380         unsigned int avs_vertical_block_number;
 381         /* r7.7: 0 */
 382         unsigned int group_id_number;
 383     } grf7;
 384
 385     struct {
 386         unsigned int padx[8];
 387     } grf8;
 388 };
 389
 390 struct i965_post_processing_context
 391 {
 392     int current_pp;
 393     struct pp_module pp_modules[NUM_PP_MODULES];
 394     void *pp_static_parameter;
 395     void *pp_inline_parameter;
 396
 397     struct {
 398         dri_bo *bo;
 399     } surface_state_binding_table;
 400
 401     struct {
 402         dri_bo *bo;
 403     } curbe;
 404
 405     struct {
 406         dri_bo *bo;
 407         int num_interface_descriptors;
 408     } idrt;
 409
 410     struct {
 411         dri_bo *bo;
 412     } vfe_state;
 413
 414     struct {
 415         dri_bo *bo;
 416         dri_bo *bo_8x8;
 417         dri_bo *bo_8x8_uv;
 418     } sampler_state_table;
 419
 420     struct {
 421         unsigned int size;
 422
 423         unsigned int vfe_start;
 424         unsigned int cs_start;
 425
 426         unsigned int num_vfe_entries;
 427         unsigned int num_cs_entries;
 428
 429         unsigned int size_vfe_entry;
 430         unsigned int size_cs_entry;
 431     } urb;
 432
 433     struct {
 434         dri_bo *bo;
 435     } stmm;
 436
 437     union {
 438         struct pp_load_save_context pp_load_save_context;
 439         struct pp_scaling_context pp_scaling_context;
 440         struct pp_avs_context pp_avs_context;
 441         struct pp_dndi_context pp_dndi_context;
 442         struct pp_dn_context pp_dn_context;
 443     } private_context;
 444
 445     int (*pp_x_steps)(void *private_context);
 446     int (*pp_y_steps)(void *private_context);
 447     int (*pp_set_block_parameter)(struct i965_post_processing_context *pp_context, int x, int y);
 448
 449     struct intel_batchbuffer *batch;
 450 };
 451
 452 struct i965_proc_context
 453 {
 454     struct hw_context base;
 455     struct i965_post_processing_context pp_context;
 456 };
 457
 458 VASurfaceID
 459 i965_post_processing(
 460     VADriverContextP   ctx,
 461     VASurfaceID        surface,
 462     const VARectangle *src_rect,
 463     const VARectangle *dst_rect,
 464     unsigned int       flags,
 465     int                *has_done_scaling
 466 );
 467
 468 VAStatus
 469 i965_image_processing(VADriverContextP ctx,
 470                       const struct i965_surface *src_surface,
 471                       const VARectangle *src_rect,
 472                       struct i965_surface *dst_surface,
 473                       const VARectangle *dst_rect);
 474
 475 Bool
 476 i965_post_processing_terminate(VADriverContextP ctx);
 477 Bool
 478 i965_post_processing_init(VADriverContextP ctx);
 479
 480 #endif /* __I965_POST_PROCESSING_H__ */