include/configs/suvd3.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   4  *                    Dave Liu <daveliu@freescale.com>
   5  *
   6  * Copyright (C) 2007 Logic Product Development, Inc.
   7  *                    Peter Barada <peterb@logicpd.com>
   8  *
   9  * Copyright (C) 2007 MontaVista Software, Inc.
  10  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  11  *
  12  * (C) Copyright 2010
  13  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14  */
  15
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22
  23 #define CONFIG_HOSTNAME         "suvd3"
  24 #define CONFIG_KM_BOARD_NAME   "suvd3"
  25
  26 /*
  27  * High Level Configuration Options
  28  */
  29 #define CONFIG_QE       /* Has QE */
  30 #define CONFIG_KM8321   /* Keymile PBEC8321 board specific */
  31
  32 #define CONFIG_KM_DEF_ARCH      "arch=ppc_8xx\0"
  33
  34 /* include common defines/options for all Keymile boards */
  35 #include "km/keymile-common.h"
  36 #include "km/km-powerpc.h"
  37
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN               66000000
  42 #define CONFIG_SYS_CLK_FREQ             66000000
  43 #define CONFIG_83XX_PCICLK              66000000
  44
  45 /*
  46  * IMMR new address
  47  */
  48 #define CONFIG_SYS_IMMR         0xE0000000
  49
  50 /*
  51  * Bus Arbitration Configuration Register (ACR)
  52  */
  53 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  54 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  55 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  56 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  57
  58 /*
  59  * DDR Setup
  60  */
  61 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  62 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  63 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  64
  65 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  66 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  67                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  68
  69 #define CFG_83XX_DDR_USES_CS0
  70
  71 /*
  72  * Manually set up DDR parameters
  73  */
  74 #define CONFIG_DDR_II
  75 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  76
  77 /*
  78  * The reserved memory
  79  */
  80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  81 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  82
  83 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  84 #define CONFIG_SYS_RAMBOOT
  85 #endif
  86
  87 /* Reserve 768 kB for Mon */
  88 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  89
  90 /*
  91  * Initial RAM Base Address Setup
  92  */
  93 #define CONFIG_SYS_INIT_RAM_LOCK
  94 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  95 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  96 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  97                                                 GENERATED_GBL_DATA_SIZE)
  98
  99 /*
 100  * Init Local Bus Memory Controller:
 101  *
 102  * Bank Bus     Machine PortSz  Size  Device
 103  * ---- ---     ------- ------  -----  ------
 104  *  0   Local   GPCM    16 bit  256MB FLASH
 105  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 106  *
 107  */
 108 /*
 109  * FLASH on the Local Bus
 110  */
 111 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 112
 113 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 114                                 BR_PS_16 | /* 16 bit port size */ \
 115                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 116                                 BR_V)
 117
 118 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_256MB | \
 119                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 120                                 OR_GPCM_SCY_5 | \
 121                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 122
 123 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 124 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 125 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 126
 127 /*
 128  * PRIO1/PIGGY on the local bus CS1
 129  */
 130 /* Window base at flash base */
 131 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 132                                 BR_PS_8 | /* 8 bit port size */ \
 133                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 134                                 BR_V)
 135 #define CONFIG_SYS_OR1_PRELIM   (OR_AM_128MB | \
 136                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 137                                 OR_GPCM_SCY_2 | \
 138                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 139
 140 /*
 141  * Serial Port
 142  */
 143 #define CONFIG_SYS_NS16550_SERIAL
 144 #define CONFIG_SYS_NS16550_REG_SIZE     1
 145 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 146
 147 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 148 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 149
 150 /*
 151  * QE UEC ethernet configuration
 152  */
 153 #define CONFIG_UEC_ETH
 154 #define CONFIG_ETHPRIME         "UEC0"
 155
 156 #define CONFIG_UEC_ETH1         /* GETH1 */
 157 #define UEC_VERBOSE_DEBUG       1
 158
 159 #ifdef CONFIG_UEC_ETH1
 160 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 161 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 162 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 163 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 164 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 165 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 166 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 167 #endif
 168
 169 /*
 170  * Environment
 171  */
 172
 173 #ifndef CONFIG_SYS_RAMBOOT
 174 #ifndef CONFIG_ENV_ADDR
 175 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 176                                         CONFIG_SYS_MONITOR_LEN)
 177 #endif
 178 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 179 #ifndef CONFIG_ENV_OFFSET
 180 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 181 #endif
 182
 183 /* Address and size of Redundant Environment Sector     */
 184 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 185                                                 CONFIG_ENV_SECT_SIZE)
 186 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 187
 188 #else /* CFG_SYS_RAMBOOT */
 189 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 190 #define CONFIG_ENV_SIZE         0x2000
 191 #endif /* CFG_SYS_RAMBOOT */
 192
 193 /* I2C */
 194 #define CONFIG_SYS_I2C
 195 #define CONFIG_SYS_NUM_I2C_BUSES        4
 196 #define CONFIG_SYS_I2C_MAX_HOPS         1
 197 #define CONFIG_SYS_I2C_FSL
 198 #define CONFIG_SYS_FSL_I2C_SPEED        200000
 199 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 200 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 201 #define CONFIG_SYS_I2C_OFFSET           0x3000
 202 #define CONFIG_SYS_FSL_I2C2_SPEED       200000
 203 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 204 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 205 #define CONFIG_SYS_I2C_BUSES    {{0, {I2C_NULL_HOP} }, \
 206                 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
 207                 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
 208                 {1, {I2C_NULL_HOP} } }
 209
 210 #define CONFIG_KM_IVM_BUS               2       /* I2C2 (Mux-Port 1)*/
 211
 212 #if defined(CONFIG_CMD_NAND)
 213 #define CONFIG_NAND_KMETER1
 214 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 215 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 216 #endif
 217
 218 /*
 219  * For booting Linux, the board info and command line data
 220  * have to be in the first 8 MB of memory, since this is
 221  * the maximum mapped by the Linux kernel during initialization.
 222  */
 223 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 224
 225 /*
 226  * Core HID Setup
 227  */
 228 #define CONFIG_SYS_HID0_INIT            0x000000000
 229 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 230                                          HID0_ENABLE_INSTRUCTION_CACHE)
 231 #define CONFIG_SYS_HID2                 HID2_HBE
 232
 233 /*
 234  * Internal Definitions
 235  */
 236 #define BOOTFLASH_START 0xF0000000
 237
 238 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 239
 240 /*
 241  * Environment Configuration
 242  */
 243 #define CONFIG_ENV_OVERWRITE
 244 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 245 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 246 #endif
 247
 248 #ifndef CONFIG_KM_DEF_ARCH
 249 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 250 #endif
 251
 252 #define CONFIG_EXTRA_ENV_SETTINGS \
 253         CONFIG_KM_DEF_ENV                                               \
 254         CONFIG_KM_DEF_ARCH                                              \
 255         "newenv="                                                       \
 256                 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && "  \
 257                 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0"         \
 258         "unlock=yes\0"                                                  \
 259         ""
 260
 261 #if defined(CONFIG_UEC_ETH)
 262 #define CONFIG_HAS_ETH0
 263 #endif
 264
 265 /*
 266  * System IO Config
 267  */
 268 #define CONFIG_SYS_SICRL        SICRL_IRQ_CKS
 269
 270 #define CONFIG_SYS_DDRCDR (\
 271         DDRCDR_EN | \
 272         DDRCDR_PZ_MAXZ | \
 273         DDRCDR_NZ_MAXZ | \
 274         DDRCDR_M_ODR)
 275
 276 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 277 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 278                                          SDRAM_CFG_32_BE | \
 279                                          SDRAM_CFG_SREN | \
 280                                          SDRAM_CFG_HSE)
 281
 282 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 283 #define CONFIG_SYS_DDR_CLK_CNTL         (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 284 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 285                                  (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
 286
 287 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 288                                          CSCONFIG_ODT_WR_CFG | \
 289                                          CSCONFIG_ROW_BIT_13 | \
 290                                          CSCONFIG_COL_BIT_10)
 291
 292 #define CONFIG_SYS_DDR_MODE     0x47860242
 293 #define CONFIG_SYS_DDR_MODE2    0x8080c000
 294
 295 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 296                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 297                                  (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 298                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 299                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 300                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 301                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 302                                  (0 << TIMING_CFG0_RWT_SHIFT))
 303
 304 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
 305                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 306                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 307                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 308                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 309                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 310                                  (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 311                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 312
 313 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 314                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 315                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 316                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 317                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 318                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 319                                  (5 << TIMING_CFG2_CPO_SHIFT))
 320
 321 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 322
 323 #define CONFIG_SYS_KMBEC_FPGA_BASE      0xE8000000
 324 #define CONFIG_SYS_KMBEC_FPGA_SIZE      128
 325
 326 /* EEprom support */
 327 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 328
 329 /*
 330  * Local Bus Configuration & Clock Setup
 331  */
 332 #define CONFIG_SYS_LCRR_DBYP    0x80000000
 333 #define CONFIG_SYS_LCRR_EADC    0x00010000
 334 #define CONFIG_SYS_LCRR_CLKDIV  0x00000002
 335
 336 #define CONFIG_SYS_LBC_LBCR     0x00000000
 337
 338 #define CONFIG_SYS_APP1_BASE            0xA0000000
 339 #define CONFIG_SYS_APP1_SIZE            256 /* Megabytes */
 340 #define CONFIG_SYS_APP2_BASE            0xB0000000
 341 #define CONFIG_SYS_APP2_SIZE            256 /* Megabytes */
 342
 343 /* EEprom support */
 344 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 345
 346 /*
 347  * Init Local Bus Memory Controller:
 348  *
 349  * Bank Bus     Machine PortSz  Size  Device
 350  * ---- ---     ------- ------  -----  ------
 351  *  2   Local   UPMA    16 bit  256MB APP1
 352  *  3   Local   GPCM    16 bit  256MB APP2
 353  *
 354  */
 355
 356 /*
 357  * APP1 on the local bus CS2
 358  */
 359 #define CONFIG_SYS_BR2_PRELIM   (CONFIG_SYS_APP1_BASE | \
 360                                  BR_PS_16 | \
 361                                  BR_MS_UPMA | \
 362                                  BR_V)
 363 #define CONFIG_SYS_OR2_PRELIM   (OR_AM_256MB)
 364
 365 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_APP2_BASE | \
 366                                  BR_PS_16 | \
 367                                  BR_V)
 368
 369 #define CONFIG_SYS_OR3_PRELIM   (OR_AM_256MB | \
 370                                  OR_GPCM_CSNT | \
 371                                  OR_GPCM_ACS_DIV4 | \
 372                                  OR_GPCM_SCY_3 | \
 373                                  OR_GPCM_TRLX_SET)
 374
 375 #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \
 376                          0x0000c000 | \
 377                          MxMR_WLFx_2X)
 378 #endif /* __CONFIG_H */