include/configs/sbc8349.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * WindRiver SBC8349 U-Boot configuration file.
   4  * Copyright (c) 2006, 2007 Wind River Systems, Inc.
   5  *
   6  * Paul Gortmaker <paul.gortmaker@windriver.com>
   7  * Based on the MPC8349EMDS config.
   8  */
   9
  10 /*
  11  * sbc8349 board configuration file.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  */
  20 #define CONFIG_E300             1       /* E300 Family */
  21
  22 /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */
  23 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  24
  25 #define CONFIG_SYS_IMMR         0xE0000000
  26
  27 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  28 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  29 #define CONFIG_SYS_MEMTEST_END          0x00100000
  30
  31 /*
  32  * DDR Setup
  33  */
  34 #undef CONFIG_DDR_ECC                   /* only for ECC DDR module */
  35 #undef CONFIG_DDR_ECC_CMD               /* use DDR ECC user commands */
  36 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  37 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* WRS; Fsl board uses CS2/CS3 */
  38
  39 /*
  40  * 32-bit data path mode.
  41  *
  42  * Please note that using this mode for devices with the real density of 64-bit
  43  * effectively reduces the amount of available memory due to the effect of
  44  * wrapping around while translating address to row/columns, for example in the
  45  * 256MB module the upper 128MB get aliased with contents of the lower
  46  * 128MB); normally this define should be used for devices with real 32-bit
  47  * data path.
  48  */
  49 #undef CONFIG_DDR_32BIT
  50
  51 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory*/
  52 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  53 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  54 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  55                                 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  56 #define CONFIG_DDR_2T_TIMING
  57
  58 #if defined(CONFIG_SPD_EEPROM)
  59 /*
  60  * Determine DDR configuration from I2C interface.
  61  */
  62 #define SPD_EEPROM_ADDRESS      0x52            /* DDR DIMM */
  63
  64 #else
  65 /*
  66  * Manually set up DDR parameters
  67  * NB: manual DDR setup untested on sbc834x
  68  */
  69 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  70 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  71                                         | CSCONFIG_ROW_BIT_13 \
  72                                         | CSCONFIG_COL_BIT_10)
  73 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  74 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  75 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
  76 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
  77
  78 #if defined(CONFIG_DDR_32BIT)
  79 /* set burst length to 8 for 32-bit data path */
  80                                 /* DLL,normal,seq,4/2.5, 8 burst len */
  81 #define CONFIG_SYS_DDR_MODE     0x00000023
  82 #else
  83 /* the default burst length is 4 - for 64-bit data path */
  84                                 /* DLL,normal,seq,4/2.5, 4 burst len */
  85 #define CONFIG_SYS_DDR_MODE     0x00000022
  86 #endif
  87 #endif
  88
  89 /*
  90  * SDRAM on the Local Bus
  91  */
  92 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
  93 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
  94
  95 /*
  96  * FLASH on the Local Bus
  97  */
  98 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
  99 #define CONFIG_SYS_FLASH_SIZE           8               /* flash size in MB */
 100
 101 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE \
 102                                         | BR_PS_16      /* 16 bit port */ \
 103                                         | BR_MS_GPCM    /* MSEL = GPCM */ \
 104                                         | BR_V)         /* valid */
 105
 106 #define CONFIG_SYS_OR0_PRELIM           (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 107                                         | OR_GPCM_XAM \
 108                                         | OR_GPCM_CSNT \
 109                                         | OR_GPCM_ACS_DIV2 \
 110                                         | OR_GPCM_XACS \
 111                                         | OR_GPCM_SCY_15 \
 112                                         | OR_GPCM_TRLX_SET \
 113                                         | OR_GPCM_EHTR_SET \
 114                                         | OR_GPCM_EAD)
 115                                         /* 0xFF806FF7 */
 116
 117                                         /* window base at flash base */
 118 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 119 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_8MB)
 120
 121 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 122 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* sectors per device */
 123
 124 #undef CONFIG_SYS_FLASH_CHECKSUM
 125 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 126 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 127
 128 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 129
 130 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 131 #define CONFIG_SYS_RAMBOOT
 132 #else
 133 #undef  CONFIG_SYS_RAMBOOT
 134 #endif
 135
 136 #define CONFIG_SYS_INIT_RAM_LOCK        1
 137                                         /* Initial RAM address */
 138 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000
 139                                         /* Size of used area in RAM*/
 140 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 141
 142 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 143                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 144 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 145
 146 #define CONFIG_SYS_MONITOR_LEN  (256 * 1024)    /* Reserve 256 kB for Mon */
 147 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 148
 149 /*
 150  * Local Bus LCRR and LBCR regs
 151  *    LCRR:  DLL bypass, Clock divider is 4
 152  * External Local Bus rate is
 153  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 154  */
 155 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 156 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 157 #define CONFIG_SYS_LBC_LBCR     0x00000000
 158
 159 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 160
 161 #ifdef CONFIG_SYS_LB_SDRAM
 162 /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/
 163 /*
 164  * Base Register 2 and Option Register 2 configure SDRAM.
 165  * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 166  *
 167  * For BR2, need:
 168  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 169  *    port-size = 32-bits = BR2[19:20] = 11
 170  *    no parity checking = BR2[21:22] = 00
 171  *    SDRAM for MSEL = BR2[24:26] = 011
 172  *    Valid = BR[31] = 1
 173  *
 174  * 0    4    8    12   16   20   24   28
 175  * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
 176  */
 177
 178 #define CONFIG_SYS_BR2_PRELIM           (CONFIG_SYS_LBC_SDRAM_BASE \
 179                                         | BR_PS_32 \
 180                                         | BR_MS_SDRAM \
 181                                         | BR_V)
 182                                         /* 0xF0001861 */
 183 #define CONFIG_SYS_LBLAWBAR2_PRELIM     CONFIG_SYS_LBC_SDRAM_BASE
 184 #define CONFIG_SYS_LBLAWAR2_PRELIM      (LBLAWAR_EN | LBLAWAR_64MB)
 185
 186 /*
 187  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 188  *
 189  * For OR2, need:
 190  *    64MB mask for AM, OR2[0:7] = 1111 1100
 191  *                 XAM, OR2[17:18] = 11
 192  *    9 columns OR2[19-21] = 010
 193  *    13 rows   OR2[23-25] = 100
 194  *    EAD set for extra time OR[31] = 1
 195  *
 196  * 0    4    8    12   16   20   24   28
 197  * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
 198  */
 199
 200 #define CONFIG_SYS_OR2_PRELIM   (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \
 201                         | OR_SDRAM_XAM \
 202                         | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
 203                         | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
 204                         | OR_SDRAM_EAD)
 205                         /* 0xFC006901 */
 206
 207                                 /* LB sdram refresh timer, about 6us */
 208 #define CONFIG_SYS_LBC_LSRT     0x32000000
 209                                 /* LB refresh timer prescal, 266MHz/32 */
 210 #define CONFIG_SYS_LBC_MRTPR    0x20000000
 211
 212 #define CONFIG_SYS_LBC_LSDMR_COMMON     (LSDMR_RFEN \
 213                                         | LSDMR_BSMA1516 \
 214                                         | LSDMR_RFCR8 \
 215                                         | LSDMR_PRETOACT6 \
 216                                         | LSDMR_ACTTORW3 \
 217                                         | LSDMR_BL8 \
 218                                         | LSDMR_WRC3 \
 219                                         | LSDMR_CL3)
 220
 221 /*
 222  * SDRAM Controller configuration sequence.
 223  */
 224 #define CONFIG_SYS_LBC_LSDMR_1  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
 225 #define CONFIG_SYS_LBC_LSDMR_2  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 226 #define CONFIG_SYS_LBC_LSDMR_3  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
 227 #define CONFIG_SYS_LBC_LSDMR_4  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
 228 #define CONFIG_SYS_LBC_LSDMR_5  (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
 229 #endif
 230
 231 /*
 232  * Serial Port
 233  */
 234 #define CONFIG_SYS_NS16550_SERIAL
 235 #define CONFIG_SYS_NS16550_REG_SIZE    1
 236 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 237
 238 #define CONFIG_SYS_BAUDRATE_TABLE  \
 239                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 240
 241 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 242 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 243
 244 /* I2C */
 245 #define CONFIG_SYS_I2C
 246 #define CONFIG_SYS_I2C_FSL
 247 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 248 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 249 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 250 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 251 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 252 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 253 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69}, {1, 0x69} }
 254 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 255
 256 /* TSEC */
 257 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 258 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 259 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 260 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 261
 262 /*
 263  * General PCI
 264  * Addresses are mapped 1-1.
 265  */
 266 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 267 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 268 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 269 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 270 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 271 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 272 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 273 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 274 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 275
 276 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 277 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 278 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 279 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 280 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 281 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 282 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 283 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 284 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 285
 286 #if defined(CONFIG_PCI)
 287
 288 #undef CONFIG_EEPRO100
 289 #undef CONFIG_TULIP
 290
 291 #if !defined(CONFIG_PCI_PNP)
 292         #define PCI_ENET0_IOADDR        0xFIXME
 293         #define PCI_ENET0_MEMADDR       0xFIXME
 294         #define PCI_IDSEL_NUMBER        0xFIXME
 295 #endif
 296
 297 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 298 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 299
 300 #endif  /* CONFIG_PCI */
 301
 302 /*
 303  * TSEC configuration
 304  */
 305
 306 #if defined(CONFIG_TSEC_ENET)
 307
 308 #define CONFIG_TSEC1    1
 309 #define CONFIG_TSEC1_NAME       "TSEC0"
 310 #define CONFIG_TSEC2    1
 311 #define CONFIG_TSEC2_NAME       "TSEC1"
 312 #define CONFIG_PHY_BCM5421S     1
 313 #define TSEC1_PHY_ADDR          0x19
 314 #define TSEC2_PHY_ADDR          0x1a
 315 #define TSEC1_PHYIDX            0
 316 #define TSEC2_PHYIDX            0
 317 #define TSEC1_FLAGS             TSEC_GIGABIT
 318 #define TSEC2_FLAGS             TSEC_GIGABIT
 319
 320 /* Options are: TSEC[0-1] */
 321 #define CONFIG_ETHPRIME         "TSEC0"
 322
 323 #endif  /* CONFIG_TSEC_ENET */
 324
 325 /*
 326  * Environment
 327  */
 328 #ifndef CONFIG_SYS_RAMBOOT
 329         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0x40000)
 330         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 331         #define CONFIG_ENV_SIZE         0x2000
 332
 333 /* Address and size of Redundant Environment Sector     */
 334 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 335 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 336
 337 #else
 338         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 339         #define CONFIG_ENV_SIZE         0x2000
 340 #endif
 341
 342 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 343 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 344
 345 /*
 346  * BOOTP options
 347  */
 348 #define CONFIG_BOOTP_BOOTFILESIZE
 349
 350 /*
 351  * Command line configuration.
 352  */
 353
 354 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 355
 356 /*
 357  * Miscellaneous configurable options
 358  */
 359 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 360
 361 /*
 362  * For booting Linux, the board info and command line data
 363  * have to be in the first 256 MB of memory, since this is
 364  * the maximum mapped by the Linux kernel during initialization.
 365  */
 366                                 /* Initial Memory map for Linux*/
 367 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 368
 369 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 370
 371 /* System IO Config */
 372 #define CONFIG_SYS_SICRH 0
 373 #define CONFIG_SYS_SICRL SICRL_LDP_A
 374
 375 #define CONFIG_SYS_HID0_INIT    0x000000000
 376 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 377                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 378
 379 /* #define CONFIG_SYS_HID0_FINAL        (\
 380         HID0_ENABLE_INSTRUCTION_CACHE |\
 381         HID0_ENABLE_M_BIT |\
 382         HID0_ENABLE_ADDRESS_BROADCAST) */
 383
 384 #define CONFIG_SYS_HID2 HID2_HBE
 385
 386 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 387
 388 /* DDR @ 0x00000000 */
 389 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 390                                 | BATL_PP_RW \
 391                                 | BATL_MEMCOHERENCE)
 392 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 393                                 | BATU_BL_256M \
 394                                 | BATU_VS \
 395                                 | BATU_VP)
 396
 397 /* PCI @ 0x80000000 */
 398 #ifdef CONFIG_PCI
 399 #define CONFIG_PCI_INDIRECT_BRIDGE
 400 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_PCI1_MEM_BASE \
 401                                 | BATL_PP_RW \
 402                                 | BATL_MEMCOHERENCE)
 403 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_PCI1_MEM_BASE \
 404                                 | BATU_BL_256M \
 405                                 | BATU_VS \
 406                                 | BATU_VP)
 407 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PCI1_MMIO_BASE \
 408                                 | BATL_PP_RW \
 409                                 | BATL_CACHEINHIBIT \
 410                                 | BATL_GUARDEDSTORAGE)
 411 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PCI1_MMIO_BASE \
 412                                 | BATU_BL_256M \
 413                                 | BATU_VS \
 414                                 | BATU_VP)
 415 #else
 416 #define CONFIG_SYS_IBAT1L       (0)
 417 #define CONFIG_SYS_IBAT1U       (0)
 418 #define CONFIG_SYS_IBAT2L       (0)
 419 #define CONFIG_SYS_IBAT2U       (0)
 420 #endif
 421
 422 #ifdef CONFIG_MPC83XX_PCI2
 423 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI2_MEM_BASE \
 424                                 | BATL_PP_RW \
 425                                 | BATL_MEMCOHERENCE)
 426 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI2_MEM_BASE \
 427                                 | BATU_BL_256M \
 428                                 | BATU_VS \
 429                                 | BATU_VP)
 430 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI2_MMIO_BASE \
 431                                 | BATL_PP_RW \
 432                                 | BATL_CACHEINHIBIT \
 433                                 | BATL_GUARDEDSTORAGE)
 434 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI2_MMIO_BASE \
 435                                 | BATU_BL_256M \
 436                                 | BATU_VS \
 437                                 | BATU_VP)
 438 #else
 439 #define CONFIG_SYS_IBAT3L       (0)
 440 #define CONFIG_SYS_IBAT3U       (0)
 441 #define CONFIG_SYS_IBAT4L       (0)
 442 #define CONFIG_SYS_IBAT4U       (0)
 443 #endif
 444
 445 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
 446 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_IMMR \
 447                                 | BATL_PP_RW \
 448                                 | BATL_CACHEINHIBIT \
 449                                 | BATL_GUARDEDSTORAGE)
 450 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_IMMR \
 451                                 | BATU_BL_256M \
 452                                 | BATU_VS \
 453                                 | BATU_VP)
 454
 455 /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
 456 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_LBC_SDRAM_BASE \
 457                                 | BATL_PP_RW \
 458                                 | BATL_MEMCOHERENCE \
 459                                 | BATL_GUARDEDSTORAGE)
 460 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_LBC_SDRAM_BASE \
 461                                 | BATU_BL_256M \
 462                                 | BATU_VS \
 463                                 | BATU_VP)
 464
 465 #define CONFIG_SYS_IBAT7L       (0)
 466 #define CONFIG_SYS_IBAT7U       (0)
 467
 468 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 469 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 470 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 471 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 472 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 473 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 474 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 475 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 476 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 477 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 478 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 479 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 480 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 481 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 482 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 483 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 484
 485 #if defined(CONFIG_CMD_KGDB)
 486 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 487 #endif
 488
 489 /*
 490  * Environment Configuration
 491  */
 492 #define CONFIG_ENV_OVERWRITE
 493
 494 #if defined(CONFIG_TSEC_ENET)
 495 #define CONFIG_HAS_ETH0
 496 #define CONFIG_HAS_ETH1
 497 #endif
 498
 499 #define CONFIG_HOSTNAME         "SBC8349"
 500 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 501 #define CONFIG_BOOTFILE         "uImage"
 502
 503                                 /* default location for tftp and bootm */
 504 #define CONFIG_LOADADDR         800000
 505
 506 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 507         "netdev=eth0\0"                                                 \
 508         "hostname=sbc8349\0"                                            \
 509         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 510                 "nfsroot=${serverip}:${rootpath}\0"                     \
 511         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 512         "addip=setenv bootargs ${bootargs} "                            \
 513                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 514                 ":${hostname}:${netdev}:off panic=1\0"                  \
 515         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 516         "flash_nfs=run nfsargs addip addtty;"                           \
 517                 "bootm ${kernel_addr}\0"                                \
 518         "flash_self=run ramargs addip addtty;"                          \
 519                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 520         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 521                 "bootm\0"                                               \
 522         "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
 523         "update=protect off ff800000 ff83ffff; "                        \
 524                 "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
 525         "upd=run load update\0"                                         \
 526         "fdtaddr=780000\0"                                              \
 527         "fdtfile=sbc8349.dtb\0"                                         \
 528         ""
 529
 530 #define CONFIG_NFSBOOTCOMMAND                                           \
 531         "setenv bootargs root=/dev/nfs rw "                             \
 532                 "nfsroot=$serverip:$rootpath "                          \
 533                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 534                                                         "$netdev:off "  \
 535                 "console=$consoledev,$baudrate $othbootargs;"           \
 536         "tftp $loadaddr $bootfile;"                                     \
 537         "tftp $fdtaddr $fdtfile;"                                       \
 538         "bootm $loadaddr - $fdtaddr"
 539
 540 #define CONFIG_RAMBOOTCOMMAND                                           \
 541         "setenv bootargs root=/dev/ram rw "                             \
 542                 "console=$consoledev,$baudrate $othbootargs;"           \
 543         "tftp $ramdiskaddr $ramdiskfile;"                               \
 544         "tftp $loadaddr $bootfile;"                                     \
 545         "tftp $fdtaddr $fdtfile;"                                       \
 546         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 547
 548 #define CONFIG_BOOTCOMMAND      "run flash_self"
 549
 550 #endif  /* __CONFIG_H */