1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2020 Hitachi ABB Power Grids
6 #ifndef __CONFIG_PG_WCOM_EXPU1_H
7 #define __CONFIG_PG_WCOM_EXPU1_H
11 /* CLIPS FPGA Definitions */
12 #define CFG_SYS_CSPR3_EXT (0x00)
13 #define CFG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CLIPS_BASE) | \
17 #define CFG_SYS_AMASK3 IFC_AMASK(64 * 1024)
18 #define CFG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \
20 #define CFG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \
21 FTIM0_GPCM_TEADC(0x7) | \
22 FTIM0_GPCM_TEAHC(0x2))
23 #define CFG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \
24 FTIM1_GPCM_TRAD(0x12))
25 #define CFG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \
26 FTIM2_GPCM_TCH(0x1) | \
28 #define CFG_SYS_CS3_FTIM3 0x04000000
31 #define WCOM_CLIPS_RST 0
32 #define WCOM_QSFP_RST 1
33 #define WCOM_PHY_RST 2
34 #define WCOM_TMG_RST 3
35 #define KM_DBG_ETH_RST 15
37 /* QRIO GPIOs used for deblocking */
38 #define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A
39 #define KM_I2C_DEBLOCK_SCL 20
40 #define KM_I2C_DEBLOCK_SDA 21
43 #define WCOM_ZL30343_CFG_ADDR 0xe8070000
44 #define WCOM_ZL30343_SPI_BUS 0
45 #define WCOM_ZL30343_CS 0
47 #include "km/pg-wcom-ls102xa.h"
49 #endif /* __CONFIG_PG_WCOM_EXPU1_H */