include/configs/ls2080ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2019-2021 NXP
   4  * Copyright 2015 Freescale Semiconductor
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2080a_common.h"
  11
  12 #ifdef CONFIG_FSL_QSPI
  13 #ifdef CONFIG_TARGET_LS2081ARDB
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #endif
  17
  18 #define I2C_MUX_CH_VOL_MONITOR          0xa
  19 #define I2C_VOL_MONITOR_ADDR            0x38
  20 #define CONFIG_VOL_MONITOR_IR36021_READ
  21 #define CONFIG_VOL_MONITOR_IR36021_SET
  22
  23 #define CONFIG_VID_FLS_ENV              "ls2080ardb_vdd_mv"
  24 #ifndef CONFIG_SPL_BUILD
  25 #define CONFIG_VID
  26 #endif
  27 /* step the IR regulator in 5mV increments */
  28 #define IR_VDD_STEP_DOWN                5
  29 #define IR_VDD_STEP_UP                  5
  30 /* The lowest and highest voltage allowed for LS2080ARDB */
  31 #define VDD_MV_MIN                      819
  32 #define VDD_MV_MAX                      1212
  33
  34 #ifndef __ASSEMBLY__
  35 unsigned long get_board_sys_clk(void);
  36 #endif
  37
  38 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  39 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  40
  41 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  42 #define SPD_EEPROM_ADDRESS1     0x51
  43 #define SPD_EEPROM_ADDRESS2     0x52
  44 #define SPD_EEPROM_ADDRESS3     0x53
  45 #define SPD_EEPROM_ADDRESS4     0x54
  46 #define SPD_EEPROM_ADDRESS5     0x55
  47 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  48 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  49 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  50 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  51 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  52 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  53 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  54 #endif
  55
  56 /* SATA */
  57 #define CONFIG_SCSI_AHCI_PLAT
  58
  59 #define CONFIG_SYS_SATA1                        AHCI_BASE_ADDR1
  60 #define CONFIG_SYS_SATA2                        AHCI_BASE_ADDR2
  61
  62 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
  63 #define CONFIG_SYS_SCSI_MAX_LUN                 1
  64 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  65                                                 CONFIG_SYS_SCSI_MAX_LUN)
  66
  67 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
  68
  69 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  70 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  71 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  72
  73 #define CONFIG_SYS_NOR0_CSPR                                    \
  74         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  75         CSPR_PORT_SIZE_16                                       | \
  76         CSPR_MSEL_NOR                                           | \
  77         CSPR_V)
  78 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  79         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  80         CSPR_PORT_SIZE_16                                       | \
  81         CSPR_MSEL_NOR                                           | \
  82         CSPR_V)
  83 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  84 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  85                                 FTIM0_NOR_TEADC(0x5) | \
  86                                 FTIM0_NOR_TEAHC(0x5))
  87 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  88                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  89                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  90 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  91                                 FTIM2_NOR_TCH(0x4) | \
  92                                 FTIM2_NOR_TWPH(0x0E) | \
  93                                 FTIM2_NOR_TWP(0x1c))
  94 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  95 #define CONFIG_SYS_IFC_CCR      0x01000000
  96
  97 #ifdef CONFIG_MTD_NOR_FLASH
  98 #define CONFIG_SYS_FLASH_QUIET_TEST
  99 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 100
 101 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 102 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 103 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 104 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 105
 106 #define CONFIG_SYS_FLASH_EMPTY_INFO
 107 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
 108                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
 109 #endif
 110
 111 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 112 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 113
 114 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 115 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 116                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 117                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 118                                 | CSPR_V)
 119 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 120
 121 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 122                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 123                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 124                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 125                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 126                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 127                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 128
 129 /* ONFI NAND Flash mode0 Timing Params */
 130 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 131                                         FTIM0_NAND_TWP(0x30)   | \
 132                                         FTIM0_NAND_TWCHT(0x0e) | \
 133                                         FTIM0_NAND_TWH(0x14))
 134 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 135                                         FTIM1_NAND_TWBE(0xab)  | \
 136                                         FTIM1_NAND_TRR(0x1c)   | \
 137                                         FTIM1_NAND_TRP(0x30))
 138 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 139                                         FTIM2_NAND_TREH(0x14) | \
 140                                         FTIM2_NAND_TWHRE(0x3c))
 141 #define CONFIG_SYS_NAND_FTIM3           0x0
 142
 143 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 144 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 145 #define CONFIG_MTD_NAND_VERIFY_WRITE
 146
 147 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 148 #define QIXIS_LBMAP_SWITCH              0x06
 149 #define QIXIS_LBMAP_MASK                0x0f
 150 #define QIXIS_LBMAP_SHIFT               0
 151 #define QIXIS_LBMAP_DFLTBANK            0x00
 152 #define QIXIS_LBMAP_ALTBANK             0x04
 153 #define QIXIS_LBMAP_NAND                0x09
 154 #define QIXIS_RST_CTL_RESET             0x31
 155 #define QIXIS_RST_CTL_RESET_EN          0x30
 156 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 157 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 158 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 159 #define QIXIS_RCW_SRC_NAND              0x119
 160 #define QIXIS_RST_FORCE_MEM             0x01
 161
 162 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 163 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 164                                 | CSPR_PORT_SIZE_8 \
 165                                 | CSPR_MSEL_GPCM \
 166                                 | CSPR_V)
 167 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 168                                 | CSPR_PORT_SIZE_8 \
 169                                 | CSPR_MSEL_GPCM \
 170                                 | CSPR_V)
 171
 172 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 173 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 174 /* QIXIS Timing parameters for IFC CS3 */
 175 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 176                                         FTIM0_GPCM_TEADC(0x0e) | \
 177                                         FTIM0_GPCM_TEAHC(0x0e))
 178 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 179                                         FTIM1_GPCM_TRAD(0x3f))
 180 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 181                                         FTIM2_GPCM_TCH(0xf) | \
 182                                         FTIM2_GPCM_TWP(0x3E))
 183 #define CONFIG_SYS_CS3_FTIM3            0x0
 184
 185 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
 186 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 187 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 188 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 189 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 190 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 191 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 192 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 193 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 194 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 195 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 196 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 197 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 198 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 199 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 200 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 201 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 202 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 203
 204 #define CONFIG_SPL_PAD_TO               0x80000
 205 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 206 #else
 207 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 208 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 209 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 210 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 211 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 212 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 213 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 214 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 215 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 216 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 217 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 218 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 219 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 220 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 221 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 222 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 223 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 224 #endif
 225
 226 /* Debug Server firmware */
 227 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 228 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 229 #endif
 230 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 231
 232 #ifdef CONFIG_TARGET_LS2081ARDB
 233 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 234 #define QIXIS_QMAP_MASK                 0x07
 235 #define QIXIS_QMAP_SHIFT                5
 236 #define QIXIS_LBMAP_DFLTBANK            0x00
 237 #define QIXIS_LBMAP_QSPI                0x00
 238 #define QIXIS_RCW_SRC_QSPI              0x62
 239 #define QIXIS_LBMAP_ALTBANK             0x20
 240 #define QIXIS_RST_CTL_RESET             0x31
 241 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 242 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 243 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 244 #define QIXIS_LBMAP_MASK                0x0f
 245 #define QIXIS_RST_CTL_RESET_EN          0x30
 246 #endif
 247
 248 /*
 249  * I2C
 250  */
 251 #ifdef CONFIG_TARGET_LS2081ARDB
 252 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 253 #endif
 254 #define I2C_MUX_PCA_ADDR                0x75
 255 #define I2C_MUX_PCA_ADDR_PRI            0x75 /* Primary Mux*/
 256
 257 /* I2C bus multiplexer */
 258 #define I2C_MUX_CH_DEFAULT      0x8
 259
 260 /* SPI */
 261
 262 /*
 263  * RTC configuration
 264  */
 265 #define RTC
 266 #ifdef CONFIG_TARGET_LS2081ARDB
 267 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 268 #else
 269 #define CONFIG_RTC_DS3231               1
 270 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 271 #endif
 272
 273 /* EEPROM */
 274 #define CONFIG_SYS_I2C_EEPROM_NXID
 275 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 276
 277 #define CONFIG_FSL_MEMAC
 278
 279 #ifdef CONFIG_PCI
 280 #define CONFIG_PCI_SCAN_SHOW
 281 #endif
 282
 283 #define BOOT_TARGET_DEVICES(func) \
 284         func(USB, usb, 0) \
 285         func(MMC, mmc, 0) \
 286         func(SCSI, scsi, 0) \
 287         func(DHCP, dhcp, na)
 288 #include <config_distro_bootcmd.h>
 289
 290 #ifdef CONFIG_TFABOOT
 291 #define QSPI_MC_INIT_CMD                                \
 292         "sf probe 0:0; "                                \
 293         "sf read 0x80640000 0x640000 0x80000; "         \
 294         "env exists secureboot && "                     \
 295         "esbc_validate 0x80640000 && "                  \
 296         "esbc_validate 0x80680000; "                    \
 297         "sf read 0x80a00000 0xa00000 0x200000; "        \
 298         "sf read 0x80e00000 0xe00000 0x100000; "        \
 299         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 300 #define SD_MC_INIT_CMD                          \
 301         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 302         "mmc read 0x80e00000 0x7000 0x800;"     \
 303         "env exists secureboot && "             \
 304         "mmc read 0x80640000 0x3200 0x20 && "   \
 305         "mmc read 0x80680000 0x3400 0x20 && "   \
 306         "esbc_validate 0x80640000 && "          \
 307         "esbc_validate 0x80680000 ;"            \
 308         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 309 #define IFC_MC_INIT_CMD                         \
 310         "env exists secureboot && "     \
 311         "esbc_validate 0x580640000 && "         \
 312         "esbc_validate 0x580680000; "           \
 313         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 314 #else
 315 #ifdef CONFIG_QSPI_BOOT
 316 #define MC_INIT_CMD                                     \
 317         "mcinitcmd=sf probe 0:0; "                      \
 318         "sf read 0x80640000 0x640000 0x80000; "         \
 319         "env exists secureboot && "                     \
 320         "esbc_validate 0x80640000 && "                  \
 321         "esbc_validate 0x80680000; "                    \
 322         "sf read 0x80a00000 0xa00000 0x200000; "        \
 323         "sf read 0x80e00000 0xe00000 0x100000; "        \
 324         "fsl_mc start mc 0x80a00000 0x80e00000 \0"
 325 #elif defined(CONFIG_SD_BOOT)
 326 #define MC_INIT_CMD                             \
 327         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
 328         "mmc read 0x80e00000 0x7000 0x800;"     \
 329         "env exists secureboot && "             \
 330         "mmc read 0x80640000 0x3200 0x20 && "   \
 331         "mmc read 0x80680000 0x3400 0x20 && "   \
 332         "esbc_validate 0x80640000 && "          \
 333         "esbc_validate 0x80680000 ;"            \
 334         "fsl_mc start mc 0x80a00000 0x80e00000\0" \
 335         "mcmemsize=0x70000000\0"
 336 #else
 337 #define MC_INIT_CMD                             \
 338         "mcinitcmd=env exists secureboot && "   \
 339         "esbc_validate 0x580640000 && "         \
 340         "esbc_validate 0x580680000; "           \
 341         "fsl_mc start mc 0x580a00000 0x580e00000 \0"
 342 #endif
 343 #endif
 344
 345 /* Initial environment variables */
 346 #undef CONFIG_EXTRA_ENV_SETTINGS
 347 #ifdef CONFIG_TFABOOT
 348 #define CONFIG_EXTRA_ENV_SETTINGS               \
 349         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 350         "ramdisk_addr=0x800000\0"               \
 351         "ramdisk_size=0x2000000\0"              \
 352         "fdt_high=0xa0000000\0"                 \
 353         "initrd_high=0xffffffffffffffff\0"      \
 354         "fdt_addr=0x64f00000\0"                 \
 355         "kernel_addr=0x581000000\0"             \
 356         "kernel_start=0x1000000\0"              \
 357         "kernelheader_start=0x800000\0"         \
 358         "scriptaddr=0x80000000\0"               \
 359         "scripthdraddr=0x80080000\0"            \
 360         "fdtheader_addr_r=0x80100000\0"         \
 361         "kernelheader_addr_r=0x80200000\0"      \
 362         "kernelheader_addr=0x580600000\0"       \
 363         "kernel_addr_r=0x81000000\0"            \
 364         "kernelheader_size=0x40000\0"           \
 365         "fdt_addr_r=0x90000000\0"               \
 366         "load_addr=0xa0000000\0"                \
 367         "kernel_size=0x2800000\0"               \
 368         "kernel_addr_sd=0x8000\0"               \
 369         "kernel_size_sd=0x14000\0"              \
 370         "console=ttyAMA0,38400n8\0"             \
 371         "mcmemsize=0x70000000\0"                \
 372         "sd_bootcmd=echo Trying load from SD ..;" \
 373         "mmcinfo; mmc read $load_addr "         \
 374         "$kernel_addr_sd $kernel_size_sd && "   \
 375         "bootm $load_addr#$board\0"             \
 376         QSPI_MC_INIT_CMD                                \
 377         BOOTENV                                 \
 378         "boot_scripts=ls2088ardb_boot.scr\0"    \
 379         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 380         "scan_dev_for_boot_part="               \
 381                 "part list ${devtype} ${devnum} devplist; "     \
 382                 "env exists devplist || setenv devplist 1; "    \
 383                 "for distro_bootpart in ${devplist}; do "       \
 384                         "if fstype ${devtype} "                 \
 385                                 "${devnum}:${distro_bootpart} " \
 386                                 "bootfstype; then "             \
 387                                 "run scan_dev_for_boot; "       \
 388                         "fi; "                                  \
 389                 "done\0"                                        \
 390         "boot_a_script="                                        \
 391                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 392                         "${scriptaddr} ${prefix}${script}; "    \
 393                 "env exists secureboot && load ${devtype} "     \
 394                         "${devnum}:${distro_bootpart} "         \
 395                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 396                         "&& esbc_validate ${scripthdraddr};"    \
 397                 "source ${scriptaddr}\0"                        \
 398         "qspi_bootcmd=echo Trying load from qspi..;"            \
 399                 "sf probe && sf read $load_addr "               \
 400                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 401                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 402                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 403                 " bootm $load_addr#$board\0"                    \
 404         "nor_bootcmd=echo Trying load from nor..;"              \
 405                 "cp.b $kernel_addr $load_addr "                 \
 406                 "$kernel_size ; env exists secureboot && "      \
 407                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 408                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 409                 "bootm $load_addr#$board\0"
 410 #else
 411 #define CONFIG_EXTRA_ENV_SETTINGS               \
 412         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 413         "ramdisk_addr=0x800000\0"               \
 414         "ramdisk_size=0x2000000\0"              \
 415         "fdt_high=0xa0000000\0"                 \
 416         "initrd_high=0xffffffffffffffff\0"      \
 417         "fdt_addr=0x64f00000\0"                 \
 418         "kernel_addr=0x581000000\0"             \
 419         "kernel_start=0x1000000\0"              \
 420         "kernelheader_start=0x600000\0"         \
 421         "scriptaddr=0x80000000\0"               \
 422         "scripthdraddr=0x80080000\0"            \
 423         "fdtheader_addr_r=0x80100000\0"         \
 424         "kernelheader_addr_r=0x80200000\0"      \
 425         "kernelheader_addr=0x580600000\0"       \
 426         "kernel_addr_r=0x81000000\0"            \
 427         "kernelheader_size=0x40000\0"           \
 428         "fdt_addr_r=0x90000000\0"               \
 429         "load_addr=0xa0000000\0"                \
 430         "kernel_size=0x2800000\0"               \
 431         "kernel_addr_sd=0x8000\0"               \
 432         "kernel_size_sd=0x14000\0"              \
 433         "console=ttyAMA0,38400n8\0"             \
 434         "mcmemsize=0x70000000\0"                \
 435         "sd_bootcmd=echo Trying load from SD ..;" \
 436         "mmcinfo; mmc read $load_addr "         \
 437         "$kernel_addr_sd $kernel_size_sd && "   \
 438         "bootm $load_addr#$board\0"             \
 439         MC_INIT_CMD                             \
 440         BOOTENV                                 \
 441         "boot_scripts=ls2088ardb_boot.scr\0"    \
 442         "boot_script_hdr=hdr_ls2088ardb_bs.out\0"       \
 443         "scan_dev_for_boot_part="               \
 444                 "part list ${devtype} ${devnum} devplist; "     \
 445                 "env exists devplist || setenv devplist 1; "    \
 446                 "for distro_bootpart in ${devplist}; do "       \
 447                         "if fstype ${devtype} "                 \
 448                                 "${devnum}:${distro_bootpart} " \
 449                                 "bootfstype; then "             \
 450                                 "run scan_dev_for_boot; "       \
 451                         "fi; "                                  \
 452                 "done\0"                                        \
 453         "boot_a_script="                                        \
 454                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 455                         "${scriptaddr} ${prefix}${script}; "    \
 456                 "env exists secureboot && load ${devtype} "     \
 457                         "${devnum}:${distro_bootpart} "         \
 458                         "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
 459                         "env exists secureboot "        \
 460                         "&& esbc_validate ${scripthdraddr};"    \
 461                 "source ${scriptaddr}\0"                        \
 462         "qspi_bootcmd=echo Trying load from qspi..;"            \
 463                 "sf probe && sf read $load_addr "               \
 464                 "$kernel_start $kernel_size ; env exists secureboot &&" \
 465                 "sf read $kernelheader_addr_r $kernelheader_start "     \
 466                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 467                 " bootm $load_addr#$board\0"                    \
 468         "nor_bootcmd=echo Trying load from nor..;"              \
 469                 "cp.b $kernel_addr $load_addr "                 \
 470                 "$kernel_size ; env exists secureboot && "      \
 471                 "cp.b $kernelheader_addr $kernelheader_addr_r " \
 472                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 473                 "bootm $load_addr#$board\0"
 474 #endif
 475
 476 #ifdef CONFIG_TFABOOT
 477 #define QSPI_NOR_BOOTCOMMAND                                            \
 478                         "sf probe 0:0; "                                \
 479                         "sf read 0x806c0000 0x6c0000 0x40000; "         \
 480                         "env exists mcinitcmd && env exists secureboot "\
 481                         "&& esbc_validate 0x806c0000; "                 \
 482                         "sf read 0x80d00000 0xd00000 0x100000; "        \
 483                         "env exists mcinitcmd && "                      \
 484                         "fsl_mc lazyapply dpl 0x80d00000; "             \
 485                         "run distro_bootcmd;run qspi_bootcmd; "         \
 486                         "env exists secureboot && esbc_halt;"
 487
 488 /* Try to boot an on-SD kernel first, then do normal distro boot */
 489 #define SD_BOOTCOMMAND                                          \
 490                         "env exists mcinitcmd && env exists secureboot "\
 491                         "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
 492                         "&& esbc_validate $load_addr; "                 \
 493                         "env exists mcinitcmd && run mcinitcmd "        \
 494                         "&& mmc read 0x80d00000 0x6800 0x800 "          \
 495                         "&& fsl_mc lazyapply dpl 0x80d00000; "          \
 496                         "run distro_bootcmd;run sd_bootcmd; "           \
 497                         "env exists secureboot && esbc_halt;"
 498
 499 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 500 #define IFC_NOR_BOOTCOMMAND                                             \
 501                         "env exists mcinitcmd && env exists secureboot "\
 502                         "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
 503                         "&& fsl_mc lazyapply dpl 0x580d00000;"          \
 504                         "run distro_bootcmd;run nor_bootcmd; "          \
 505                         "env exists secureboot && esbc_halt;"
 506 #else
 507 #ifdef CONFIG_QSPI_BOOT
 508 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 509 #elif defined(CONFIG_SD_BOOT)
 510 /* Try to boot an on-SD kernel first, then do normal distro boot */
 511 #else
 512 /* Try to boot an on-NOR kernel first, then do normal distro boot */
 513 #endif
 514 #endif
 515
 516 /* MAC/PHY configuration */
 517 #define CORTINA_PHY_ADDR1       0x10
 518 #define CORTINA_PHY_ADDR2       0x11
 519 #define CORTINA_PHY_ADDR3       0x12
 520 #define CORTINA_PHY_ADDR4       0x13
 521 #define AQ_PHY_ADDR1            0x00
 522 #define AQ_PHY_ADDR2            0x01
 523 #define AQ_PHY_ADDR3            0x02
 524 #define AQ_PHY_ADDR4            0x03
 525 #define AQR405_IRQ_MASK         0x36
 526 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 527
 528 #include <asm/fsl_secure_boot.h>
 529
 530 #endif /* __LS2_RDB_H */