1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2019-2021 NXP
4 * Copyright 2015 Freescale Semiconductor
10 #include "ls2080a_common.h"
12 #define I2C_MUX_CH_VOL_MONITOR 0xa
13 #define I2C_VOL_MONITOR_ADDR 0x38
15 /* step the IR regulator in 5mV increments */
16 #define IR_VDD_STEP_DOWN 5
17 #define IR_VDD_STEP_UP 5
18 /* The lowest and highest voltage allowed for LS2080ARDB */
19 #define VDD_MV_MIN 819
20 #define VDD_MV_MAX 1212
22 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
24 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
25 #define SPD_EEPROM_ADDRESS1 0x51
26 #define SPD_EEPROM_ADDRESS2 0x52
27 #define SPD_EEPROM_ADDRESS3 0x53
28 #define SPD_EEPROM_ADDRESS4 0x54
29 #define SPD_EEPROM_ADDRESS5 0x55
30 #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
31 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
33 #if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT)
35 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
36 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
37 #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
39 #define CONFIG_SYS_NOR0_CSPR \
40 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
44 #define CONFIG_SYS_NOR0_CSPR_EARLY \
45 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
49 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
50 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
51 FTIM0_NOR_TEADC(0x5) | \
53 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
54 FTIM1_NOR_TRAD_NOR(0x1a) |\
55 FTIM1_NOR_TSEQRAD_NOR(0x13))
56 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
57 FTIM2_NOR_TCH(0x4) | \
58 FTIM2_NOR_TWPH(0x0E) | \
60 #define CONFIG_SYS_NOR_FTIM3 0x04000000
61 #define CONFIG_SYS_IFC_CCR 0x01000000
63 #ifdef CONFIG_MTD_NOR_FLASH
64 #define CONFIG_SYS_FLASH_QUIET_TEST
65 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
67 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
68 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
69 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
71 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
72 CONFIG_SYS_FLASH_BASE + 0x40000000}
75 #define CONFIG_SYS_NAND_MAX_ECCPOS 256
76 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
78 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
79 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
80 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
81 | CSPR_MSEL_NAND /* MSEL = NAND */ \
83 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
85 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
86 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
87 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
88 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
89 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
90 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
91 | CSOR_NAND_PB(128)) /* Pages Per Block 128*/
93 /* ONFI NAND Flash mode0 Timing Params */
94 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \
95 FTIM0_NAND_TWP(0x30) | \
96 FTIM0_NAND_TWCHT(0x0e) | \
98 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \
99 FTIM1_NAND_TWBE(0xab) | \
100 FTIM1_NAND_TRR(0x1c) | \
101 FTIM1_NAND_TRP(0x30))
102 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \
103 FTIM2_NAND_TREH(0x14) | \
104 FTIM2_NAND_TWHRE(0x3c))
105 #define CONFIG_SYS_NAND_FTIM3 0x0
107 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
108 #define CONFIG_SYS_MAX_NAND_DEVICE 1
109 #define CONFIG_MTD_NAND_VERIFY_WRITE
111 #define QIXIS_LBMAP_SWITCH 0x06
112 #define QIXIS_LBMAP_MASK 0x0f
113 #define QIXIS_LBMAP_SHIFT 0
114 #define QIXIS_LBMAP_DFLTBANK 0x00
115 #define QIXIS_LBMAP_ALTBANK 0x04
116 #define QIXIS_LBMAP_NAND 0x09
117 #define QIXIS_RST_CTL_RESET 0x31
118 #define QIXIS_RST_CTL_RESET_EN 0x30
119 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
120 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
121 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
122 #define QIXIS_RCW_SRC_NAND 0x119
123 #define QIXIS_RST_FORCE_MEM 0x01
125 #define CONFIG_SYS_CSPR3_EXT (0x0)
126 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
130 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
135 #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
136 #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
137 /* QIXIS Timing parameters for IFC CS3 */
138 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
139 FTIM0_GPCM_TEADC(0x0e) | \
140 FTIM0_GPCM_TEAHC(0x0e))
141 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
142 FTIM1_GPCM_TRAD(0x3f))
143 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
144 FTIM2_GPCM_TCH(0xf) | \
145 FTIM2_GPCM_TWP(0x3E))
146 #define CONFIG_SYS_CS3_FTIM3 0x0
148 #if defined(CONFIG_SPL) && defined(CONFIG_MTD_RAW_NAND)
149 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
150 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY
151 #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR
152 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
153 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
154 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
155 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
156 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
157 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
158 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
159 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
160 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
161 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
162 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
163 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
164 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
165 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
167 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
169 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
170 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
171 #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
172 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
173 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
174 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
175 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
176 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
177 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
178 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
179 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
180 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
181 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
182 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
183 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
184 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
185 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
188 /* Debug Server firmware */
189 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
190 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
192 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
194 #ifdef CONFIG_TARGET_LS2081ARDB
195 #define QIXIS_QMAP_MASK 0x07
196 #define QIXIS_QMAP_SHIFT 5
197 #define QIXIS_LBMAP_DFLTBANK 0x00
198 #define QIXIS_LBMAP_QSPI 0x00
199 #define QIXIS_RCW_SRC_QSPI 0x62
200 #define QIXIS_LBMAP_ALTBANK 0x20
201 #define QIXIS_RST_CTL_RESET 0x31
202 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
203 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
204 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
205 #define QIXIS_LBMAP_MASK 0x0f
206 #define QIXIS_RST_CTL_RESET_EN 0x30
212 #ifdef CONFIG_TARGET_LS2081ARDB
213 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
215 #define I2C_MUX_PCA_ADDR 0x75
216 #define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/
218 /* I2C bus multiplexer */
219 #define I2C_MUX_CH_DEFAULT 0x8
227 #ifdef CONFIG_TARGET_LS2081ARDB
228 #define CONFIG_SYS_I2C_RTC_ADDR 0x51
230 #define CONFIG_RTC_DS3231 1
231 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
235 #define CONFIG_SYS_I2C_EEPROM_NXID
236 #define CONFIG_SYS_EEPROM_BUS_NUM 0
238 #define CONFIG_FSL_MEMAC
240 #define BOOT_TARGET_DEVICES(func) \
243 func(SCSI, scsi, 0) \
245 #include <config_distro_bootcmd.h>
247 #ifdef CONFIG_TFABOOT
248 #define QSPI_MC_INIT_CMD \
250 "sf read 0x80640000 0x640000 0x80000; " \
251 "env exists secureboot && " \
252 "esbc_validate 0x80640000 && " \
253 "esbc_validate 0x80680000; " \
254 "sf read 0x80a00000 0xa00000 0x200000; " \
255 "sf read 0x80e00000 0xe00000 0x100000; " \
256 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
257 #define SD_MC_INIT_CMD \
258 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
259 "mmc read 0x80e00000 0x7000 0x800;" \
260 "env exists secureboot && " \
261 "mmc read 0x80640000 0x3200 0x20 && " \
262 "mmc read 0x80680000 0x3400 0x20 && " \
263 "esbc_validate 0x80640000 && " \
264 "esbc_validate 0x80680000 ;" \
265 "fsl_mc start mc 0x80a00000 0x80e00000\0"
266 #define IFC_MC_INIT_CMD \
267 "env exists secureboot && " \
268 "esbc_validate 0x580640000 && " \
269 "esbc_validate 0x580680000; " \
270 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
272 #ifdef CONFIG_QSPI_BOOT
273 #define MC_INIT_CMD \
274 "mcinitcmd=sf probe 0:0; " \
275 "sf read 0x80640000 0x640000 0x80000; " \
276 "env exists secureboot && " \
277 "esbc_validate 0x80640000 && " \
278 "esbc_validate 0x80680000; " \
279 "sf read 0x80a00000 0xa00000 0x200000; " \
280 "sf read 0x80e00000 0xe00000 0x100000; " \
281 "fsl_mc start mc 0x80a00000 0x80e00000 \0"
282 #elif defined(CONFIG_SD_BOOT)
283 #define MC_INIT_CMD \
284 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
285 "mmc read 0x80e00000 0x7000 0x800;" \
286 "env exists secureboot && " \
287 "mmc read 0x80640000 0x3200 0x20 && " \
288 "mmc read 0x80680000 0x3400 0x20 && " \
289 "esbc_validate 0x80640000 && " \
290 "esbc_validate 0x80680000 ;" \
291 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
292 "mcmemsize=0x70000000\0"
294 #define MC_INIT_CMD \
295 "mcinitcmd=env exists secureboot && " \
296 "esbc_validate 0x580640000 && " \
297 "esbc_validate 0x580680000; " \
298 "fsl_mc start mc 0x580a00000 0x580e00000 \0"
302 /* Initial environment variables */
303 #undef CONFIG_EXTRA_ENV_SETTINGS
304 #ifdef CONFIG_TFABOOT
305 #define CONFIG_EXTRA_ENV_SETTINGS \
306 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
307 "ramdisk_addr=0x800000\0" \
308 "ramdisk_size=0x2000000\0" \
309 "fdt_high=0xa0000000\0" \
310 "initrd_high=0xffffffffffffffff\0" \
311 "kernel_addr=0x581000000\0" \
312 "kernel_start=0x1000000\0" \
313 "kernelheader_start=0x800000\0" \
314 "scriptaddr=0x80000000\0" \
315 "scripthdraddr=0x80080000\0" \
316 "fdtheader_addr_r=0x80100000\0" \
317 "kernelheader_addr_r=0x80200000\0" \
318 "kernelheader_addr=0x580600000\0" \
319 "kernel_addr_r=0x81000000\0" \
320 "kernelheader_size=0x40000\0" \
321 "fdt_addr_r=0x90000000\0" \
322 "load_addr=0xa0000000\0" \
323 "kernel_size=0x2800000\0" \
324 "kernel_addr_sd=0x8000\0" \
325 "kernel_size_sd=0x14000\0" \
326 "console=ttyAMA0,38400n8\0" \
327 "mcmemsize=0x70000000\0" \
328 "sd_bootcmd=echo Trying load from SD ..;" \
329 "mmcinfo; mmc read $load_addr " \
330 "$kernel_addr_sd $kernel_size_sd && " \
331 "bootm $load_addr#$board\0" \
334 "boot_scripts=ls2088ardb_boot.scr\0" \
335 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
336 "scan_dev_for_boot_part=" \
337 "part list ${devtype} ${devnum} devplist; " \
338 "env exists devplist || setenv devplist 1; " \
339 "for distro_bootpart in ${devplist}; do " \
340 "if fstype ${devtype} " \
341 "${devnum}:${distro_bootpart} " \
342 "bootfstype; then " \
343 "run scan_dev_for_boot; " \
347 "load ${devtype} ${devnum}:${distro_bootpart} " \
348 "${scriptaddr} ${prefix}${script}; " \
349 "env exists secureboot && load ${devtype} " \
350 "${devnum}:${distro_bootpart} " \
351 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
352 "&& esbc_validate ${scripthdraddr};" \
353 "source ${scriptaddr}\0" \
354 "qspi_bootcmd=echo Trying load from qspi..;" \
355 "sf probe && sf read $load_addr " \
356 "$kernel_start $kernel_size ; env exists secureboot &&" \
357 "sf read $kernelheader_addr_r $kernelheader_start " \
358 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
359 " bootm $load_addr#$board\0" \
360 "nor_bootcmd=echo Trying load from nor..;" \
361 "cp.b $kernel_addr $load_addr " \
362 "$kernel_size ; env exists secureboot && " \
363 "cp.b $kernelheader_addr $kernelheader_addr_r " \
364 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
365 "bootm $load_addr#$board\0"
367 #define CONFIG_EXTRA_ENV_SETTINGS \
368 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
369 "ramdisk_addr=0x800000\0" \
370 "ramdisk_size=0x2000000\0" \
371 "fdt_high=0xa0000000\0" \
372 "initrd_high=0xffffffffffffffff\0" \
373 "kernel_addr=0x581000000\0" \
374 "kernel_start=0x1000000\0" \
375 "kernelheader_start=0x600000\0" \
376 "scriptaddr=0x80000000\0" \
377 "scripthdraddr=0x80080000\0" \
378 "fdtheader_addr_r=0x80100000\0" \
379 "kernelheader_addr_r=0x80200000\0" \
380 "kernelheader_addr=0x580600000\0" \
381 "kernel_addr_r=0x81000000\0" \
382 "kernelheader_size=0x40000\0" \
383 "fdt_addr_r=0x90000000\0" \
384 "load_addr=0xa0000000\0" \
385 "kernel_size=0x2800000\0" \
386 "kernel_addr_sd=0x8000\0" \
387 "kernel_size_sd=0x14000\0" \
388 "console=ttyAMA0,38400n8\0" \
389 "mcmemsize=0x70000000\0" \
390 "sd_bootcmd=echo Trying load from SD ..;" \
391 "mmcinfo; mmc read $load_addr " \
392 "$kernel_addr_sd $kernel_size_sd && " \
393 "bootm $load_addr#$board\0" \
396 "boot_scripts=ls2088ardb_boot.scr\0" \
397 "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \
398 "scan_dev_for_boot_part=" \
399 "part list ${devtype} ${devnum} devplist; " \
400 "env exists devplist || setenv devplist 1; " \
401 "for distro_bootpart in ${devplist}; do " \
402 "if fstype ${devtype} " \
403 "${devnum}:${distro_bootpart} " \
404 "bootfstype; then " \
405 "run scan_dev_for_boot; " \
409 "load ${devtype} ${devnum}:${distro_bootpart} " \
410 "${scriptaddr} ${prefix}${script}; " \
411 "env exists secureboot && load ${devtype} " \
412 "${devnum}:${distro_bootpart} " \
413 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
414 "env exists secureboot " \
415 "&& esbc_validate ${scripthdraddr};" \
416 "source ${scriptaddr}\0" \
417 "qspi_bootcmd=echo Trying load from qspi..;" \
418 "sf probe && sf read $load_addr " \
419 "$kernel_start $kernel_size ; env exists secureboot &&" \
420 "sf read $kernelheader_addr_r $kernelheader_start " \
421 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
422 " bootm $load_addr#$board\0" \
423 "nor_bootcmd=echo Trying load from nor..;" \
424 "cp.b $kernel_addr $load_addr " \
425 "$kernel_size ; env exists secureboot && " \
426 "cp.b $kernelheader_addr $kernelheader_addr_r " \
427 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
428 "bootm $load_addr#$board\0"
431 #ifdef CONFIG_TFABOOT
432 #define QSPI_NOR_BOOTCOMMAND \
434 "sf read 0x806c0000 0x6c0000 0x40000; " \
435 "env exists mcinitcmd && env exists secureboot "\
436 "&& esbc_validate 0x806c0000; " \
437 "sf read 0x80d00000 0xd00000 0x100000; " \
438 "env exists mcinitcmd && " \
439 "fsl_mc lazyapply dpl 0x80d00000; " \
440 "run distro_bootcmd;run qspi_bootcmd; " \
441 "env exists secureboot && esbc_halt;"
443 /* Try to boot an on-SD kernel first, then do normal distro boot */
444 #define SD_BOOTCOMMAND \
445 "env exists mcinitcmd && env exists secureboot "\
446 "&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
447 "&& esbc_validate $load_addr; " \
448 "env exists mcinitcmd && run mcinitcmd " \
449 "&& mmc read 0x80d00000 0x6800 0x800 " \
450 "&& fsl_mc lazyapply dpl 0x80d00000; " \
451 "run distro_bootcmd;run sd_bootcmd; " \
452 "env exists secureboot && esbc_halt;"
454 /* Try to boot an on-NOR kernel first, then do normal distro boot */
455 #define IFC_NOR_BOOTCOMMAND \
456 "env exists mcinitcmd && env exists secureboot "\
457 "&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
458 "&& fsl_mc lazyapply dpl 0x580d00000;" \
459 "run distro_bootcmd;run nor_bootcmd; " \
460 "env exists secureboot && esbc_halt;"
462 #ifdef CONFIG_QSPI_BOOT
463 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
464 #elif defined(CONFIG_SD_BOOT)
465 /* Try to boot an on-SD kernel first, then do normal distro boot */
467 /* Try to boot an on-NOR kernel first, then do normal distro boot */
471 /* MAC/PHY configuration */
472 #define CORTINA_PHY_ADDR1 0x10
473 #define CORTINA_PHY_ADDR2 0x11
474 #define CORTINA_PHY_ADDR3 0x12
475 #define CORTINA_PHY_ADDR4 0x13
476 #define AQ_PHY_ADDR1 0x00
477 #define AQ_PHY_ADDR2 0x01
478 #define AQ_PHY_ADDR3 0x02
479 #define AQ_PHY_ADDR4 0x03
480 #define AQR405_IRQ_MASK 0x36
482 #include <asm/fsl_secure_boot.h>
484 #endif /* __LS2_RDB_H */