include/configs/ls1088ardb.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017, 2020-2021 NXP
   4  */
   5
   6 #ifndef __LS1088A_RDB_H
   7 #define __LS1088A_RDB_H
   8
   9 #include "ls1088a_common.h"
  10
  11 #if defined(CONFIG_TFABOOT) || \
  12         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  13 #ifndef CONFIG_SPL_BUILD
  14 #define CONFIG_QIXIS_I2C_ACCESS
  15 #endif
  16 #define SYS_NO_FLASH
  17 #endif
  18
  19 #define CONFIG_SYS_CLK_FREQ             100000000
  20 #define COUNTER_FREQUENCY_REAL          25000000        /* 25MHz */
  21 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  22
  23 #ifdef CONFIG_EMU
  24 #define CONFIG_SYS_FSL_DDR_EMU
  25 #else
  26 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  27 #endif
  28 #define SPD_EEPROM_ADDRESS      0x51
  29 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  30 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  31
  32
  33 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  34 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  35 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
  36 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64 * 1024 * 1024)
  37
  38 #define CONFIG_SYS_NOR0_CSPR                                    \
  39         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  40         CSPR_PORT_SIZE_16                                       | \
  41         CSPR_MSEL_NOR                                           | \
  42         CSPR_V)
  43 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  44         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  45         CSPR_PORT_SIZE_16                                       | \
  46         CSPR_MSEL_NOR                                           | \
  47         CSPR_V)
  48 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(6)
  49 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x1) | \
  50                                 FTIM0_NOR_TEADC(0x1) | \
  51                                 FTIM0_NOR_TEAHC(0x1))
  52 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1) | \
  53                                 FTIM1_NOR_TRAD_NOR(0x1))
  54 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x0) | \
  55                                 FTIM2_NOR_TCH(0x0) | \
  56                                 FTIM2_NOR_TWP(0x1))
  57 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  58 #define CONFIG_SYS_IFC_CCR      0x01000000
  59
  60 #ifndef SYS_NO_FLASH
  61 #define CONFIG_SYS_FLASH_QUIET_TEST
  62 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  63
  64 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  65 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  66 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  67 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  68
  69 #define CONFIG_SYS_FLASH_EMPTY_INFO
  70 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
  71 #endif
  72 #endif
  73
  74 #ifndef SPL_NO_IFC
  75 #define CONFIG_NAND_FSL_IFC
  76 #endif
  77
  78 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  79 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  80
  81 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  82 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  83                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  84                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
  85                                 | CSPR_V)
  86 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
  87
  88 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
  89                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
  90                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
  91                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
  92                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
  93                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  94                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
  95
  96 #define CONFIG_SYS_NAND_ONFI_DETECTION
  97
  98 /* ONFI NAND Flash mode0 Timing Params */
  99 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 100                                         FTIM0_NAND_TWP(0x18)   | \
 101                                         FTIM0_NAND_TWCHT(0x07) | \
 102                                         FTIM0_NAND_TWH(0x0a))
 103 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 104                                         FTIM1_NAND_TWBE(0x39)  | \
 105                                         FTIM1_NAND_TRR(0x0e)   | \
 106                                         FTIM1_NAND_TRP(0x18))
 107 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 108                                         FTIM2_NAND_TREH(0x0a) | \
 109                                         FTIM2_NAND_TWHRE(0x1e))
 110 #define CONFIG_SYS_NAND_FTIM3           0x0
 111
 112 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 113 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 114 #define CONFIG_MTD_NAND_VERIFY_WRITE
 115
 116 #ifndef SPL_NO_QIXIS
 117 #define CONFIG_FSL_QIXIS
 118 #endif
 119
 120 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 121 #define QIXIS_BRDCFG4_OFFSET            0x54
 122 #define QIXIS_LBMAP_SWITCH              2
 123 #define QIXIS_QMAP_MASK                 0xe0
 124 #define QIXIS_QMAP_SHIFT                5
 125 #define QIXIS_LBMAP_MASK                0x1f
 126 #define QIXIS_LBMAP_SHIFT               5
 127 #define QIXIS_LBMAP_DFLTBANK            0x00
 128 #define QIXIS_LBMAP_ALTBANK             0x20
 129 #define QIXIS_LBMAP_SD                  0x00
 130 #define QIXIS_LBMAP_EMMC                0x00
 131 #define QIXIS_LBMAP_SD_QSPI             0x00
 132 #define QIXIS_LBMAP_QSPI                0x00
 133 #define QIXIS_RCW_SRC_SD                0x40
 134 #define QIXIS_RCW_SRC_EMMC              0x41
 135 #define QIXIS_RCW_SRC_QSPI              0x62
 136 #define QIXIS_RST_CTL_RESET             0x31
 137 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 138 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 139 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 140 #define QIXIS_RST_FORCE_MEM             0x01
 141
 142 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 143 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 144                                         | CSPR_PORT_SIZE_8 \
 145                                         | CSPR_MSEL_GPCM \
 146                                         | CSPR_V)
 147 #define SYS_FPGA_CSPR_FINAL     (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 148                                         | CSPR_PORT_SIZE_8 \
 149                                         | CSPR_MSEL_GPCM \
 150                                         | CSPR_V)
 151
 152 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64*1024)
 153 #define CONFIG_SYS_FPGA_CSOR            CSOR_GPCM_ADM_SHIFT(0)
 154 /* QIXIS Timing parameters*/
 155 #define SYS_FPGA_CS_FTIM0       (FTIM0_GPCM_TACSE(0x0e) | \
 156                                         FTIM0_GPCM_TEADC(0x0e) | \
 157                                         FTIM0_GPCM_TEAHC(0x0e))
 158 #define SYS_FPGA_CS_FTIM1       (FTIM1_GPCM_TACO(0xff) | \
 159                                         FTIM1_GPCM_TRAD(0x3f))
 160 #define SYS_FPGA_CS_FTIM2       (FTIM2_GPCM_TCS(0xf) | \
 161                                         FTIM2_GPCM_TCH(0xf) | \
 162                                         FTIM2_GPCM_TWP(0x3E))
 163 #define SYS_FPGA_CS_FTIM3       0x0
 164
 165 #if defined(CONFIG_TFABOOT) || \
 166         defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 167 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 168 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 169 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 170 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 171 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 172 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 173 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 174 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 175 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 176 #define CONFIG_SYS_CSPR2                CONFIG_SYS_FPGA_CSPR
 177 #define CONFIG_SYS_CSPR2_FINAL          SYS_FPGA_CSPR_FINAL
 178 #define CONFIG_SYS_AMASK2               CONFIG_SYS_FPGA_AMASK
 179 #define CONFIG_SYS_CSOR2                CONFIG_SYS_FPGA_CSOR
 180 #define CONFIG_SYS_CS2_FTIM0            SYS_FPGA_CS_FTIM0
 181 #define CONFIG_SYS_CS2_FTIM1            SYS_FPGA_CS_FTIM1
 182 #define CONFIG_SYS_CS2_FTIM2            SYS_FPGA_CS_FTIM2
 183 #define CONFIG_SYS_CS2_FTIM3            SYS_FPGA_CS_FTIM3
 184 #else
 185 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 186 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 187 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 188 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 189 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 190 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 191 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 192 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 193 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 194 #endif
 195
 196 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 197
 198 #define I2C_MUX_CH_VOL_MONITOR         0xA
 199 /* Voltage monitor on channel 2*/
 200 #define I2C_VOL_MONITOR_ADDR           0x63
 201 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 202 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 203 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 204 #define I2C_SVDD_MONITOR_ADDR           0x4F
 205
 206 #define CONFIG_VID_FLS_ENV              "ls1088ardb_vdd_mv"
 207 #define CONFIG_VID
 208
 209 /* The lowest and highest voltage allowed for LS1088ARDB */
 210 #define VDD_MV_MIN                      819
 211 #define VDD_MV_MAX                      1212
 212
 213 #define CONFIG_VOL_MONITOR_LTC3882_SET
 214 #define CONFIG_VOL_MONITOR_LTC3882_READ
 215
 216 #define PWM_CHANNEL0                    0x0
 217
 218 /*
 219  * I2C bus multiplexer
 220  */
 221 #define I2C_MUX_PCA_ADDR_PRI            0x77
 222 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 223 #define I2C_RETIMER_ADDR                0x18
 224 #define I2C_MUX_CH_DEFAULT              0x8
 225 #define I2C_MUX_CH5                     0xD
 226
 227 #ifndef SPL_NO_RTC
 228 /*
 229 * RTC configuration
 230 */
 231 #define RTC
 232 #define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 233 #endif
 234
 235 /* EEPROM */
 236 #define CONFIG_SYS_I2C_EEPROM_NXID
 237 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 238
 239 #ifdef CONFIG_SPL_BUILD
 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 241 #else
 242 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 243 #endif
 244
 245 #define CONFIG_FSL_MEMAC
 246
 247 #ifndef SPL_NO_ENV
 248 /* Initial environment variables */
 249 #ifdef CONFIG_TFABOOT
 250 #define QSPI_MC_INIT_CMD                                \
 251         "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"    \
 252         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 253         "env exists secureboot && "                     \
 254         "sf read 0x80640000 0x640000 0x40000 && "       \
 255         "sf read 0x80680000 0x680000 0x40000 && "       \
 256         "esbc_validate 0x80640000 && "                  \
 257         "esbc_validate 0x80680000 ;"                    \
 258         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 259 #define SD_MC_INIT_CMD                          \
 260         "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"            \
 261         "mmc read 0x80e00000 0x7000 0x800;"                             \
 262         "env exists secureboot && "                     \
 263         "mmc read 0x80640000 0x3200 0x20 && "           \
 264         "mmc read 0x80680000 0x3400 0x20 && "           \
 265         "esbc_validate 0x80640000 && "                  \
 266         "esbc_validate 0x80680000 ;"                    \
 267         "fsl_mc start mc 0x80a00000 0x80e00000\0"
 268 #else
 269 #if defined(CONFIG_QSPI_BOOT)
 270 #define MC_INIT_CMD                             \
 271         "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;"  \
 272         "sf read 0x80e00000 0xE00000 0x100000;"                         \
 273         "env exists secureboot && "                     \
 274         "sf read 0x80640000 0x640000 0x40000 && "       \
 275         "sf read 0x80680000 0x680000 0x40000 && "       \
 276         "esbc_validate 0x80640000 && "                  \
 277         "esbc_validate 0x80680000 ;"                    \
 278         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 279         "mcmemsize=0x70000000\0"
 280 #elif defined(CONFIG_SD_BOOT)
 281 #define MC_INIT_CMD                             \
 282         "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;"          \
 283         "mmc read 0x80e00000 0x7000 0x800;"                             \
 284         "env exists secureboot && "                     \
 285         "mmc read 0x80640000 0x3200 0x20 && "           \
 286         "mmc read 0x80680000 0x3400 0x20 && "           \
 287         "esbc_validate 0x80640000 && "                  \
 288         "esbc_validate 0x80680000 ;"                    \
 289         "fsl_mc start mc 0x80a00000 0x80e00000\0"       \
 290         "mcmemsize=0x70000000\0"
 291 #endif
 292 #endif /* CONFIG_TFABOOT */
 293
 294 #undef CONFIG_EXTRA_ENV_SETTINGS
 295 #ifdef CONFIG_TFABOOT
 296 #define CONFIG_EXTRA_ENV_SETTINGS               \
 297         "BOARD=ls1088ardb\0"                    \
 298         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 299         "ramdisk_addr=0x800000\0"               \
 300         "ramdisk_size=0x2000000\0"              \
 301         "fdt_high=0xa0000000\0"                 \
 302         "initrd_high=0xffffffffffffffff\0"      \
 303         "fdt_addr=0x64f00000\0"                 \
 304         "kernel_addr=0x1000000\0"               \
 305         "kernel_addr_sd=0x8000\0"               \
 306         "kernelhdr_addr_sd=0x3000\0"            \
 307         "kernel_start=0x580100000\0"            \
 308         "kernelheader_start=0x580600000\0"      \
 309         "scriptaddr=0x80000000\0"               \
 310         "scripthdraddr=0x80080000\0"            \
 311         "fdtheader_addr_r=0x80100000\0"         \
 312         "kernelheader_addr=0x600000\0"          \
 313         "kernelheader_addr_r=0x80200000\0"      \
 314         "kernel_addr_r=0x81000000\0"            \
 315         "kernelheader_size=0x40000\0"           \
 316         "fdt_addr_r=0x90000000\0"               \
 317         "load_addr=0xa0000000\0"                \
 318         "kernel_size=0x2800000\0"               \
 319         "kernel_size_sd=0x14000\0"              \
 320         "kernelhdr_size_sd=0x20\0"              \
 321         QSPI_MC_INIT_CMD                        \
 322         "mcmemsize=0x70000000\0"                \
 323         BOOTENV                                 \
 324         "boot_scripts=ls1088ardb_boot.scr\0"    \
 325         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 326         "scan_dev_for_boot_part="               \
 327                 "part list ${devtype} ${devnum} devplist; "     \
 328                 "env exists devplist || setenv devplist 1; "    \
 329                 "for distro_bootpart in ${devplist}; do "       \
 330                         "if fstype ${devtype} "                 \
 331                                 "${devnum}:${distro_bootpart} " \
 332                                 "bootfstype; then "             \
 333                                 "run scan_dev_for_boot; "       \
 334                         "fi; "                                  \
 335                 "done\0"                                        \
 336         "boot_a_script="                                        \
 337                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 338                 "${scriptaddr} ${prefix}${script}; "            \
 339         "env exists secureboot && load ${devtype} "             \
 340                 "${devnum}:${distro_bootpart} "                 \
 341                 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
 342                 "env exists secureboot "                        \
 343                 "&& esbc_validate ${scripthdraddr};"            \
 344                 "source ${scriptaddr}\0"                        \
 345         "installer=load mmc 0:2 $load_addr "                    \
 346                 "/flex_installer_arm64.itb; "                   \
 347                 "env exists mcinitcmd && run mcinitcmd && "     \
 348                 "mmc read 0x80001000 0x6800 0x800;"             \
 349                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 350                 "bootm $load_addr#ls1088ardb\0"                 \
 351         "qspi_bootcmd=echo Trying load from qspi..;"            \
 352                 "sf probe && sf read $load_addr "               \
 353                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 354                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 355                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 356                 "bootm $load_addr#$BOARD\0"                     \
 357                 "sd_bootcmd=echo Trying load from sd card..;"           \
 358                 "mmcinfo; mmc read $load_addr "                 \
 359                 "$kernel_addr_sd $kernel_size_sd ;"             \
 360                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 361                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 362                 " && esbc_validate ${kernelheader_addr_r};"     \
 363                 "bootm $load_addr#$BOARD\0"
 364 #else
 365 #define CONFIG_EXTRA_ENV_SETTINGS               \
 366         "BOARD=ls1088ardb\0"                    \
 367         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 368         "ramdisk_addr=0x800000\0"               \
 369         "ramdisk_size=0x2000000\0"              \
 370         "fdt_high=0xa0000000\0"                 \
 371         "initrd_high=0xffffffffffffffff\0"      \
 372         "fdt_addr=0x64f00000\0"                 \
 373         "kernel_addr=0x1000000\0"               \
 374         "kernel_addr_sd=0x8000\0"               \
 375         "kernelhdr_addr_sd=0x3000\0"            \
 376         "kernel_start=0x580100000\0"            \
 377         "kernelheader_start=0x580800000\0"      \
 378         "scriptaddr=0x80000000\0"               \
 379         "scripthdraddr=0x80080000\0"            \
 380         "fdtheader_addr_r=0x80100000\0"         \
 381         "kernelheader_addr=0x600000\0"          \
 382         "kernelheader_addr_r=0x80200000\0"      \
 383         "kernel_addr_r=0x81000000\0"            \
 384         "kernelheader_size=0x40000\0"           \
 385         "fdt_addr_r=0x90000000\0"               \
 386         "load_addr=0xa0000000\0"                \
 387         "kernel_size=0x2800000\0"               \
 388         "kernel_size_sd=0x14000\0"              \
 389         "kernelhdr_size_sd=0x20\0"              \
 390         MC_INIT_CMD                             \
 391         BOOTENV                                 \
 392         "boot_scripts=ls1088ardb_boot.scr\0"    \
 393         "boot_script_hdr=hdr_ls1088ardb_bs.out\0"       \
 394         "scan_dev_for_boot_part="               \
 395                 "part list ${devtype} ${devnum} devplist; "     \
 396                 "env exists devplist || setenv devplist 1; "    \
 397                 "for distro_bootpart in ${devplist}; do "       \
 398                         "if fstype ${devtype} "                 \
 399                                 "${devnum}:${distro_bootpart} " \
 400                                 "bootfstype; then "             \
 401                                 "run scan_dev_for_boot; "       \
 402                         "fi; "                                  \
 403                 "done\0"                                        \
 404         "boot_a_script="                                        \
 405                 "load ${devtype} ${devnum}:${distro_bootpart} " \
 406                 "${scriptaddr} ${prefix}${script}; "            \
 407         "env exists secureboot && load ${devtype} "             \
 408                 "${devnum}:${distro_bootpart} "                 \
 409                 "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 410                 "&& esbc_validate ${scripthdraddr};"            \
 411                 "source ${scriptaddr}\0"                        \
 412         "installer=load mmc 0:2 $load_addr "                    \
 413                 "/flex_installer_arm64.itb; "                   \
 414                 "env exists mcinitcmd && run mcinitcmd && "     \
 415                 "mmc read 0x80001000 0x6800 0x800;"             \
 416                 "fsl_mc lazyapply dpl 0x80001000;"                      \
 417                 "bootm $load_addr#ls1088ardb\0"                 \
 418         "qspi_bootcmd=echo Trying load from qspi..;"            \
 419                 "sf probe && sf read $load_addr "               \
 420                 "$kernel_addr $kernel_size ; env exists secureboot "    \
 421                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 422                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
 423                 "bootm $load_addr#$BOARD\0"                     \
 424                 "sd_bootcmd=echo Trying load from sd card..;"           \
 425                 "mmcinfo; mmc read $load_addr "                 \
 426                 "$kernel_addr_sd $kernel_size_sd ;"             \
 427                 "env exists secureboot && mmc read $kernelheader_addr_r "\
 428                 "$kernelhdr_addr_sd $kernelhdr_size_sd "        \
 429                 " && esbc_validate ${kernelheader_addr_r};"     \
 430                 "bootm $load_addr#$BOARD\0"
 431 #endif /* CONFIG_TFABOOT */
 432
 433 #undef CONFIG_BOOTCOMMAND
 434 #ifdef CONFIG_TFABOOT
 435 #define QSPI_NOR_BOOTCOMMAND                                    \
 436         "sf read 0x80001000 0xd00000 0x100000;"         \
 437                 "env exists mcinitcmd && env exists secureboot "        \
 438                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 439                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 440                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 441                 "run distro_bootcmd;run qspi_bootcmd;"          \
 442                 "env exists secureboot && esbc_halt;"
 443 #define SD_BOOTCOMMAND                                          \
 444                 "env exists mcinitcmd && mmcinfo; "             \
 445                 "mmc read 0x80001000 0x6800 0x800; "            \
 446                 "env exists mcinitcmd && env exists secureboot "        \
 447                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 448                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 449                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 450                 "run distro_bootcmd;run sd_bootcmd;"            \
 451                 "env exists secureboot && esbc_halt;"
 452 #else
 453 #if defined(CONFIG_QSPI_BOOT)
 454 /* Try to boot an on-QSPI kernel first, then do normal distro boot */
 455 #define CONFIG_BOOTCOMMAND                                      \
 456                 "sf read 0x80001000 0xd00000 0x100000;"         \
 457                 "env exists mcinitcmd && env exists secureboot "        \
 458                 " && sf read 0x806C0000 0x6C0000 0x100000 "     \
 459                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 460                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 461                 "run distro_bootcmd;run qspi_bootcmd;"          \
 462                 "env exists secureboot && esbc_halt;"
 463
 464 /* Try to boot an on-SD kernel first, then do normal distro boot */
 465 #elif defined(CONFIG_SD_BOOT)
 466 #define CONFIG_BOOTCOMMAND                                      \
 467                 "env exists mcinitcmd && mmcinfo; "             \
 468                 "mmc read 0x80001000 0x6800 0x800; "            \
 469                 "env exists mcinitcmd && env exists secureboot "        \
 470                 " && mmc read 0x806C0000 0x3600 0x20 "          \
 471                 "&& esbc_validate 0x806C0000;env exists mcinitcmd "     \
 472                 "&& fsl_mc lazyapply dpl 0x80001000;"           \
 473                 "run distro_bootcmd;run sd_bootcmd;"            \
 474                 "env exists secureboot && esbc_halt;"
 475 #endif
 476 #endif /* CONFIG_TFABOOT */
 477
 478 /* MAC/PHY configuration */
 479 #ifdef CONFIG_FSL_MC_ENET
 480 #define AQ_PHY_ADDR1                    0x00
 481 #define AQR105_IRQ_MASK                 0x00000004
 482
 483 #define QSGMII1_PORT1_PHY_ADDR          0x0c
 484 #define QSGMII1_PORT2_PHY_ADDR          0x0d
 485 #define QSGMII1_PORT3_PHY_ADDR          0x0e
 486 #define QSGMII1_PORT4_PHY_ADDR          0x0f
 487 #define QSGMII2_PORT1_PHY_ADDR          0x1c
 488 #define QSGMII2_PORT2_PHY_ADDR          0x1d
 489 #define QSGMII2_PORT3_PHY_ADDR          0x1e
 490 #define QSGMII2_PORT4_PHY_ADDR          0x1f
 491
 492 #define CONFIG_ETHPRIME         "DPMAC1@xgmii"
 493 #define CONFIG_PHY_GIGE
 494 #endif
 495 #endif
 496
 497 #ifndef SPL_NO_ENV
 498
 499 #define BOOT_TARGET_DEVICES(func) \
 500         func(MMC, mmc, 0) \
 501         func(USB, usb, 0) \
 502         func(SCSI, scsi, 0) \
 503         func(DHCP, dhcp, na)
 504 #include <config_distro_bootcmd.h>
 505 #endif
 506
 507 #include <asm/fsl_secure_boot.h>
 508
 509 #endif /* __LS1088A_RDB_H */