1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017, 2020-2021 NXP
6 #ifndef __LS1088A_QDS_H
7 #define __LS1088A_QDS_H
9 #include "ls1088a_common.h"
11 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
15 #define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
17 #define SPD_EEPROM_ADDRESS 0x51
23 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
24 #define CFG_SYS_NOR0_CSPR_EXT (0x0)
25 #define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
26 #define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
28 #define CFG_SYS_NOR0_CSPR \
29 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS) | \
33 #define CFG_SYS_NOR0_CSPR_EARLY \
34 (CSPR_PHYS_ADDR(CFG_SYS_FLASH_BASE_PHYS_EARLY) | \
38 #define CFG_SYS_NOR1_CSPR \
39 (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS) | \
43 #define CFG_SYS_NOR1_CSPR_EARLY \
44 (CSPR_PHYS_ADDR(CFG_SYS_FLASH1_BASE_PHYS_EARLY) | \
48 #define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
49 #define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
50 FTIM0_NOR_TEADC(0x5) | \
51 FTIM0_NOR_TAVDS(0x6) | \
53 #define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
54 FTIM1_NOR_TRAD_NOR(0x1a) | \
55 FTIM1_NOR_TSEQRAD_NOR(0x13))
56 #define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
57 FTIM2_NOR_TCH(0x8) | \
58 FTIM2_NOR_TWPH(0xe) | \
60 #define CFG_SYS_NOR_FTIM3 0x04000000
61 #define CFG_SYS_IFC_CCR 0x01000000
64 #define CFG_SYS_FLASH_BANKS_LIST { CFG_SYS_FLASH_BASE,\
65 CFG_SYS_FLASH_BASE + 0x40000000}
69 #define CFG_SYS_NAND_CSPR_EXT (0x0)
70 #define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
71 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
72 | CSPR_MSEL_NAND /* MSEL = NAND */ \
74 #define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
76 #define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
77 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
78 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
79 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
80 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
81 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
82 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
84 /* ONFI NAND Flash mode0 Timing Params */
85 #define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
86 FTIM0_NAND_TWP(0x18) | \
87 FTIM0_NAND_TWCHT(0x07) | \
89 #define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
90 FTIM1_NAND_TWBE(0x39) | \
91 FTIM1_NAND_TRR(0x0e) | \
93 #define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
94 FTIM2_NAND_TREH(0x0a) | \
95 FTIM2_NAND_TWHRE(0x1e))
96 #define CFG_SYS_NAND_FTIM3 0x0
98 #define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
100 #define CFG_SYS_I2C_FPGA_ADDR 0x66
101 #define QIXIS_LBMAP_SWITCH 6
102 #define QIXIS_QMAP_MASK 0xe0
103 #define QIXIS_QMAP_SHIFT 5
104 #define QIXIS_LBMAP_MASK 0x0f
105 #define QIXIS_LBMAP_SHIFT 0
106 #define QIXIS_LBMAP_DFLTBANK 0x0e
107 #define QIXIS_LBMAP_ALTBANK 0x2e
108 #define QIXIS_LBMAP_SD 0x00
109 #define QIXIS_LBMAP_EMMC 0x00
110 #define QIXIS_LBMAP_IFC 0x00
111 #define QIXIS_LBMAP_SD_QSPI 0x0e
112 #define QIXIS_LBMAP_QSPI 0x0e
113 #define QIXIS_RCW_SRC_IFC 0x25
114 #define QIXIS_RCW_SRC_SD 0x40
115 #define QIXIS_RCW_SRC_EMMC 0x41
116 #define QIXIS_RCW_SRC_QSPI 0x62
117 #define QIXIS_RST_CTL_RESET 0x41
118 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
119 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
120 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
121 #define QIXIS_RST_FORCE_MEM 0x01
122 #define QIXIS_STAT_PRES1 0xb
123 #define QIXIS_SDID_MASK 0x07
124 #define QIXIS_ESDHC_NO_ADAPTER 0x7
126 #define CFG_SYS_FPGA_CSPR_EXT (0x0)
127 #define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
131 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
136 #define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
137 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
138 #define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
140 #define CFG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
142 /* QIXIS Timing parameters*/
143 #define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
144 FTIM0_GPCM_TEADC(0x0e) | \
145 FTIM0_GPCM_TEAHC(0x0e))
146 #define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
147 FTIM1_GPCM_TRAD(0x3f))
148 #define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
149 FTIM2_GPCM_TCH(0xf) | \
150 FTIM2_GPCM_TWP(0x3E))
151 #define SYS_FPGA_CS_FTIM3 0x0
153 #ifdef CONFIG_TFABOOT
154 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
155 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
156 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
157 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
158 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
159 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
160 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
161 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
162 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
163 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
164 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
165 #define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
166 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
167 #define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
168 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
169 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
170 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
171 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
172 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
173 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
174 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
175 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
176 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
177 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
178 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
179 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
180 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
181 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
182 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
183 #define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
184 #define CFG_SYS_AMASK3 SYS_FPGA_AMASK
185 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
186 #define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
187 #define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
188 #define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
189 #define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
191 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
192 #define CFG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
193 #define CFG_SYS_CSPR0 CFG_SYS_NAND_CSPR
194 #define CFG_SYS_AMASK0 CFG_SYS_NAND_AMASK
195 #define CFG_SYS_CSOR0 CFG_SYS_NAND_CSOR
196 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
197 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
198 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
199 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
200 #define CFG_SYS_CSPR2_EXT CFG_SYS_FPGA_CSPR_EXT
201 #define CFG_SYS_CSPR2 CFG_SYS_FPGA_CSPR
202 #define CFG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
203 #define CFG_SYS_AMASK2 SYS_FPGA_AMASK
204 #define CFG_SYS_CSOR2 CFG_SYS_FPGA_CSOR
205 #define CFG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
206 #define CFG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
207 #define CFG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
208 #define CFG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
210 #define CFG_SYS_CSPR0_EXT CFG_SYS_NOR0_CSPR_EXT
211 #define CFG_SYS_CSPR0 CFG_SYS_NOR0_CSPR_EARLY
212 #define CFG_SYS_CSPR0_FINAL CFG_SYS_NOR0_CSPR
213 #define CFG_SYS_AMASK0 CFG_SYS_NOR_AMASK
214 #define CFG_SYS_CSOR0 CFG_SYS_NOR_CSOR
215 #define CFG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
216 #define CFG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
217 #define CFG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
218 #define CFG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
219 #define CFG_SYS_CSPR1_EXT CFG_SYS_NOR0_CSPR_EXT
220 #define CFG_SYS_CSPR1 CFG_SYS_NOR1_CSPR_EARLY
221 #define CFG_SYS_CSPR1_FINAL CFG_SYS_NOR1_CSPR
222 #define CFG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
223 #define CFG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
224 #define CFG_SYS_CSOR1 CFG_SYS_NOR_CSOR
225 #define CFG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
226 #define CFG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
227 #define CFG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
228 #define CFG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
229 #define CFG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
230 #define CFG_SYS_CSPR2 CFG_SYS_NAND_CSPR
231 #define CFG_SYS_AMASK2 CFG_SYS_NAND_AMASK
232 #define CFG_SYS_CSOR2 CFG_SYS_NAND_CSOR
233 #define CFG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
234 #define CFG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
235 #define CFG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
236 #define CFG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
237 #define CFG_SYS_CSPR3_EXT CFG_SYS_FPGA_CSPR_EXT
238 #define CFG_SYS_CSPR3 CFG_SYS_FPGA_CSPR
239 #define CFG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
240 #define CFG_SYS_AMASK3 SYS_FPGA_AMASK
241 #define CFG_SYS_CSOR3 CFG_SYS_FPGA_CSOR
242 #define CFG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
243 #define CFG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
244 #define CFG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
245 #define CFG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
249 #define CFG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
252 * I2C bus multiplexer
254 #define I2C_MUX_PCA_ADDR_PRI 0x77
255 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
256 #define I2C_RETIMER_ADDR 0x18
257 #define I2C_RETIMER_ADDR2 0x19
258 #define I2C_MUX_CH_DEFAULT 0x8
259 #define I2C_MUX_CH5 0xD
261 #define I2C_MUX_CH_VOL_MONITOR 0xA
263 /* Voltage monitor on channel 2*/
264 #define I2C_VOL_MONITOR_ADDR 0x63
265 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
266 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
267 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
268 #define I2C_SVDD_MONITOR_ADDR 0x4F
270 /* The lowest and highest voltage allowed for LS1088AQDS */
271 #define VDD_MV_MIN 819
272 #define VDD_MV_MAX 1212
274 #define PWM_CHANNEL0 0x0
279 #define CFG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
281 #ifdef CONFIG_FSL_DSPI
282 #if !defined(CONFIG_TFABOOT) && \
283 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
288 "kernelheader_addr_r=0x80200000\0" \
289 "fdtheader_addr_r=0x80100000\0" \
290 "kernel_addr_r=0x81000000\0" \
291 "fdt_addr_r=0x90000000\0" \
292 "load_addr=0xa0000000\0"
294 /* Initial environment variables */
295 #ifdef CONFIG_NXP_ESBC
296 #undef CFG_EXTRA_ENV_SETTINGS
297 #define CFG_EXTRA_ENV_SETTINGS \
299 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
300 "loadaddr=0x90100000\0" \
301 "kernel_addr=0x100000\0" \
302 "ramdisk_addr=0x800000\0" \
303 "ramdisk_size=0x2000000\0" \
304 "fdt_high=0xa0000000\0" \
305 "initrd_high=0xffffffffffffffff\0" \
306 "kernel_start=0x1000000\0" \
307 "kernel_load=0xa0000000\0" \
308 "kernel_size=0x2800000\0" \
309 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x200000;" \
310 "sf read 0xa0640000 0x640000 0x4000; esbc_validate 0xa0640000;" \
311 "sf read 0xa0e00000 0xe00000 0x100000;" \
312 "sf read 0xa0680000 0x680000 0x4000;esbc_validate 0xa0680000;" \
313 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
314 "mcmemsize=0x70000000 \0"
315 #else /* if !(CONFIG_NXP_ESBC) */
316 #ifdef CONFIG_TFABOOT
317 #define QSPI_MC_INIT_CMD \
318 "sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
319 "sf read 0x80e00000 0xE00000 0x100000;" \
320 "fsl_mc start mc 0x80a00000 0x80e00000\0"
321 #define SD_MC_INIT_CMD \
322 "mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
323 "mmc read 0x80e00000 0x7000 0x800;" \
324 "fsl_mc start mc 0x80a00000 0x80e00000\0"
325 #define IFC_MC_INIT_CMD \
326 "fsl_mc start mc 0x580A00000 0x580E00000\0"
328 #undef CFG_EXTRA_ENV_SETTINGS
329 #define CFG_EXTRA_ENV_SETTINGS \
331 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
332 "loadaddr=0x90100000\0" \
333 "kernel_addr=0x100000\0" \
334 "kernel_addr_sd=0x800\0" \
335 "ramdisk_addr=0x800000\0" \
336 "ramdisk_size=0x2000000\0" \
337 "fdt_high=0xa0000000\0" \
338 "initrd_high=0xffffffffffffffff\0" \
339 "kernel_start=0x1000000\0" \
340 "kernel_start_sd=0x8000\0" \
341 "kernel_load=0xa0000000\0" \
342 "kernel_size=0x2800000\0" \
343 "kernel_size_sd=0x14000\0" \
344 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
345 "sf read 0x80e00000 0xE00000 0x100000;" \
346 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
347 "mcmemsize=0x70000000 \0" \
348 "BOARD=ls1088aqds\0" \
349 "scriptaddr=0x80000000\0" \
350 "scripthdraddr=0x80080000\0" \
352 "boot_scripts=ls1088aqds_boot.scr\0" \
353 "boot_script_hdr=hdr_ls1088aqds_bs.out\0" \
354 "scan_dev_for_boot_part=" \
355 "part list ${devtype} ${devnum} devplist; " \
356 "env exists devplist || setenv devplist 1; " \
357 "for distro_bootpart in ${devplist}; do " \
358 "if fstype ${devtype} " \
359 "${devnum}:${distro_bootpart} " \
360 "bootfstype; then " \
361 "run scan_dev_for_boot; " \
365 "load ${devtype} ${devnum}:${distro_bootpart} " \
366 "${scriptaddr} ${prefix}${script}; " \
367 "env exists secureboot && load ${devtype} " \
368 "${devnum}:${distro_bootpart} " \
369 "${scripthdraddr} ${prefix}${boot_script_hdr}; "\
370 "env exists secureboot " \
371 "&& esbc_validate ${scripthdraddr};" \
372 "source ${scriptaddr}\0" \
373 "qspi_bootcmd=echo Trying load from qspi..; " \
375 "sf read 0x80001000 0xd00000 0x100000; " \
376 "fsl_mc lazyapply dpl 0x80001000 && " \
377 "sf read $kernel_load $kernel_start " \
378 "$kernel_size && bootm $kernel_load#$BOARD\0" \
379 "sd_bootcmd=echo Trying load from sd card..; " \
380 "mmcinfo;mmc read 0x80001000 0x6800 0x800; "\
381 "fsl_mc lazyapply dpl 0x80001000 && " \
382 "mmc read $kernel_load $kernel_start_sd " \
383 "$kernel_size_sd && bootm $kernel_load#$BOARD\0" \
384 "nor_bootcmd=echo Trying load from nor..; " \
385 "fsl_mc lazyapply dpl 0x580d00000 && " \
386 "cp.b $kernel_start $kernel_load " \
387 "$kernel_size && bootm $kernel_load#$BOARD\0"
389 #if defined(CONFIG_QSPI_BOOT)
390 #undef CFG_EXTRA_ENV_SETTINGS
391 #define CFG_EXTRA_ENV_SETTINGS \
393 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
394 "loadaddr=0x90100000\0" \
395 "kernel_addr=0x100000\0" \
396 "ramdisk_addr=0x800000\0" \
397 "ramdisk_size=0x2000000\0" \
398 "fdt_high=0xa0000000\0" \
399 "initrd_high=0xffffffffffffffff\0" \
400 "kernel_start=0x1000000\0" \
401 "kernel_load=0xa0000000\0" \
402 "kernel_size=0x2800000\0" \
403 "mcinitcmd=sf probe 0:0;sf read 0x80a00000 0xA00000 0x200000;" \
404 "sf read 0x80e00000 0xE00000 0x100000;" \
405 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
406 "mcmemsize=0x70000000 \0"
407 #elif defined(CONFIG_SD_BOOT)
408 #undef CFG_EXTRA_ENV_SETTINGS
409 #define CFG_EXTRA_ENV_SETTINGS \
411 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
412 "loadaddr=0x90100000\0" \
413 "kernel_addr=0x800\0" \
414 "ramdisk_addr=0x800000\0" \
415 "ramdisk_size=0x2000000\0" \
416 "fdt_high=0xa0000000\0" \
417 "initrd_high=0xffffffffffffffff\0" \
418 "kernel_start=0x8000\0" \
419 "kernel_load=0xa0000000\0" \
420 "kernel_size=0x14000\0" \
421 "mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
422 "mmc read 0x80e00000 0x7000 0x800;" \
423 "fsl_mc start mc 0x80a00000 0x80e00000\0" \
424 "mcmemsize=0x70000000 \0"
426 #undef CFG_EXTRA_ENV_SETTINGS
427 #define CFG_EXTRA_ENV_SETTINGS \
429 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
430 "loadaddr=0x90100000\0" \
431 "kernel_addr=0x100000\0" \
432 "ramdisk_addr=0x800000\0" \
433 "ramdisk_size=0x2000000\0" \
434 "fdt_high=0xa0000000\0" \
435 "initrd_high=0xffffffffffffffff\0" \
436 "kernel_start=0x1000000\0" \
437 "kernel_load=0xa0000000\0" \
438 "kernel_size=0x2800000\0" \
439 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
440 "mcmemsize=0x70000000 \0"
442 #endif /* CONFIG_TFABOOT */
443 #endif /* CONFIG_NXP_ESBC */
445 #ifdef CONFIG_TFABOOT
446 #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
447 "env exists secureboot && esbc_halt;;"
448 #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \
449 "env exists secureboot && esbc_halt;;"
450 #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \
451 "env exists secureboot && esbc_halt;;"
454 #ifdef CONFIG_FSL_MC_ENET
455 #define RGMII_PHY1_ADDR 0x1
456 #define RGMII_PHY2_ADDR 0x2
457 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
458 #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
459 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
460 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
462 #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
463 #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
464 #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
465 #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
466 #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
467 #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
468 #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
469 #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
470 #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
471 #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
472 #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
473 #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
474 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
475 #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
476 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
477 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
481 #define BOOT_TARGET_DEVICES(func) \
484 func(SCSI, scsi, 0) \
486 #include <config_distro_bootcmd.h>
488 #include <asm/fsl_secure_boot.h>
490 #endif /* __LS1088A_QDS_H */