1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
6 #ifndef __LS1043AQDS_H__
7 #define __LS1043AQDS_H__
9 #include "ls1043a_common.h"
12 unsigned long get_board_sys_clk(void);
15 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
17 #define CONFIG_LAYERSCAPE_NS_ACCESS
19 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
20 /* Physical Memory Map */
21 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
23 #define SPD_EEPROM_ADDRESS 0x51
24 #define CONFIG_SYS_SPD_BUS_NUM 0
27 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
30 #ifdef CONFIG_SYS_DPAA_FMAN
31 #define RGMII_PHY1_ADDR 0x1
32 #define RGMII_PHY2_ADDR 0x2
33 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
34 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
35 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
36 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
37 /* PHY address on QSGMII riser card on slot 1 */
38 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
39 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
40 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
41 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
42 /* PHY address on QSGMII riser card on slot 2 */
43 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
44 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
45 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
46 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
51 #define CONFIG_LPUART_32B_REG
55 #define CONFIG_SCSI_AHCI_PLAT
58 #define CONFIG_SYS_I2C_EEPROM_NXID
59 #define CONFIG_SYS_EEPROM_BUS_NUM 0
61 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
63 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
64 #define CONFIG_SYS_SCSI_MAX_LUN 1
65 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
66 CONFIG_SYS_SCSI_MAX_LUN)
71 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
72 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
73 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
77 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
78 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
83 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
85 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
87 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
88 FTIM0_NOR_TEADC(0x5) | \
90 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
91 FTIM1_NOR_TRAD_NOR(0x1a) | \
92 FTIM1_NOR_TSEQRAD_NOR(0x13))
93 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
94 FTIM2_NOR_TCH(0x4) | \
95 FTIM2_NOR_TWPH(0xe) | \
97 #define CONFIG_SYS_NOR_FTIM3 0
99 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
100 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
101 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
102 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
104 #define CONFIG_SYS_FLASH_EMPTY_INFO
105 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
106 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
108 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
109 #define CONFIG_SYS_WRITE_SWAPPED_DATA
112 * NAND Flash Definitions
114 #define CONFIG_NAND_FSL_IFC
116 #define CONFIG_SYS_NAND_BASE 0x7e800000
117 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
119 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
121 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
125 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
126 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
127 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
128 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
129 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
130 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
131 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
132 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
134 #define CONFIG_SYS_NAND_ONFI_DETECTION
136 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
137 FTIM0_NAND_TWP(0x18) | \
138 FTIM0_NAND_TWCHT(0x7) | \
140 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
141 FTIM1_NAND_TWBE(0x39) | \
142 FTIM1_NAND_TRR(0xe) | \
143 FTIM1_NAND_TRP(0x18))
144 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
145 FTIM2_NAND_TREH(0xa) | \
146 FTIM2_NAND_TWHRE(0x1e))
147 #define CONFIG_SYS_NAND_FTIM3 0x0
149 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
150 #define CONFIG_SYS_MAX_NAND_DEVICE 1
151 #define CONFIG_MTD_NAND_VERIFY_WRITE
154 #ifdef CONFIG_NAND_BOOT
155 #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
156 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
157 #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
160 #if defined(CONFIG_TFABOOT) || \
161 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
162 #define CONFIG_QIXIS_I2C_ACCESS
168 #define CONFIG_FSL_QIXIS
170 #ifdef CONFIG_FSL_QIXIS
171 #define QIXIS_BASE 0x7fb00000
172 #define QIXIS_BASE_PHYS QIXIS_BASE
173 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
174 #define QIXIS_LBMAP_SWITCH 6
175 #define QIXIS_LBMAP_MASK 0x0f
176 #define QIXIS_LBMAP_SHIFT 0
177 #define QIXIS_LBMAP_DFLTBANK 0x00
178 #define QIXIS_LBMAP_ALTBANK 0x04
179 #define QIXIS_LBMAP_NAND 0x09
180 #define QIXIS_LBMAP_SD 0x00
181 #define QIXIS_LBMAP_SD_QSPI 0xff
182 #define QIXIS_LBMAP_QSPI 0xff
183 #define QIXIS_RCW_SRC_NAND 0x106
184 #define QIXIS_RCW_SRC_SD 0x040
185 #define QIXIS_RCW_SRC_QSPI 0x045
186 #define QIXIS_RST_CTL_RESET 0x41
187 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
188 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
189 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
191 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
192 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
196 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
197 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
198 CSOR_NOR_NOR_MODE_AVD_NOR | \
202 * QIXIS Timing parameters for IFC GPCM
204 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
205 FTIM0_GPCM_TEADC(0x20) | \
206 FTIM0_GPCM_TEAHC(0x10))
207 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
208 FTIM1_GPCM_TRAD(0x1f))
209 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
210 FTIM2_GPCM_TCH(0x8) | \
211 FTIM2_GPCM_TWP(0xf0))
212 #define CONFIG_SYS_FPGA_FTIM3 0x0
215 #ifdef CONFIG_TFABOOT
216 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
217 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
218 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
219 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
220 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
221 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
222 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
223 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
224 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
225 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
226 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
227 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
228 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
229 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
230 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
231 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
232 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
233 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
234 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
235 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
236 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
237 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
238 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
239 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
240 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
241 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
242 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
243 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
244 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
245 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
246 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
247 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
249 #ifdef CONFIG_NAND_BOOT
250 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
251 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
252 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
253 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
254 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
255 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
256 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
257 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
258 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
259 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
260 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
261 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
262 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
263 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
264 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
265 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
266 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
267 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
268 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
269 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
270 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
271 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
272 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
273 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
274 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
275 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
276 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
277 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
278 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
279 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
280 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
281 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
283 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
284 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
285 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
286 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
287 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
288 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
289 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
290 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
291 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
292 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
293 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
294 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
295 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
296 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
297 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
298 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
299 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
300 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
301 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
302 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
303 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
304 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
305 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
306 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
307 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
308 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
309 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
310 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
311 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
312 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
313 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
314 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
319 * I2C bus multiplexer
321 #define I2C_MUX_PCA_ADDR_PRI 0x77
322 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
323 #define I2C_RETIMER_ADDR 0x18
324 #define I2C_MUX_CH_DEFAULT 0x8
325 #define I2C_MUX_CH_CH7301 0xC
326 #define I2C_MUX_CH5 0xD
327 #define I2C_MUX_CH7 0xF
329 #define I2C_MUX_CH_VOL_MONITOR 0xa
331 /* Voltage monitor on channel 2*/
332 #define I2C_VOL_MONITOR_ADDR 0x40
333 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
334 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
335 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
337 #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
338 #ifndef CONFIG_SPL_BUILD
341 #define CONFIG_VOL_MONITOR_IR36021_SET
342 #define CONFIG_VOL_MONITOR_INA220
343 /* The lowest and highest voltage allowed for LS1043AQDS */
344 #define VDD_MV_MIN 819
345 #define VDD_MV_MAX 1212
348 * Miscellaneous configurable options
351 #define CONFIG_SYS_HZ 1000
353 #define CONFIG_SYS_INIT_SP_OFFSET \
354 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
356 #ifdef CONFIG_SPL_BUILD
357 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
359 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
366 #include <asm/fsl_secure_boot.h>
368 #endif /* __LS1043AQDS_H__ */