1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
5 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
11 /* KMBEC FPGA (PRIO) */
12 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
13 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64
15 #define CONFIG_HOSTNAME "kmeter1"
16 #define CONFIG_KM_BOARD_NAME "kmeter1"
17 #define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
20 * High Level Configuration Options
22 #define CONFIG_QE /* Has QE */
24 /* include common defines/options for all Keymile boards */
25 #include "km/keymile-common.h"
26 #include "km/km-powerpc.h"
31 #define CONFIG_SYS_IMMR 0xE0000000
34 * Bus Arbitration Configuration Register (ACR)
36 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
37 #define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
38 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
39 #define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
44 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
45 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
46 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
48 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
49 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
50 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
52 #define CFG_83XX_DDR_USES_CS0
55 * Manually set up DDR parameters
58 #define CONFIG_SYS_DDR_SIZE 2048 /* MB */
63 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
64 #define CONFIG_SYS_FLASH_BASE 0xF0000000
66 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
67 #define CONFIG_SYS_RAMBOOT
70 /* Reserve 768 kB for Mon */
71 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
74 * Initial RAM Base Address Setup
76 #define CONFIG_SYS_INIT_RAM_LOCK
77 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
78 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
79 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
80 GENERATED_GBL_DATA_SIZE)
83 * Init Local Bus Memory Controller:
85 * Bank Bus Machine PortSz Size Device
86 * ---- --- ------- ------ ----- ------
87 * 0 Local GPCM 16 bit 256MB FLASH
88 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
92 * FLASH on the Local Bus
94 #define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
96 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
97 BR_PS_16 | /* 16 bit port size */ \
98 BR_MS_GPCM | /* MSEL = GPCM */ \
101 #define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
102 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
104 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
106 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
107 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
108 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
111 * PRIO1/PIGGY on the local bus CS1
113 /* Window base at flash base */
114 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \
115 BR_PS_8 | /* 8 bit port size */ \
116 BR_MS_GPCM | /* MSEL = GPCM */ \
118 #define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \
119 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
121 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
126 #define CONFIG_CONS_INDEX 1
127 #define CONFIG_SYS_NS16550_SERIAL
128 #define CONFIG_SYS_NS16550_REG_SIZE 1
129 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
131 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
132 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
135 * QE UEC ethernet configuration
137 #define CONFIG_UEC_ETH
138 #define CONFIG_ETHPRIME "UEC0"
140 #define CONFIG_UEC_ETH1 /* GETH1 */
141 #define UEC_VERBOSE_DEBUG 1
143 #ifdef CONFIG_UEC_ETH1
144 #define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
145 #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
146 #define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
147 #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
148 #define CONFIG_SYS_UEC1_PHY_ADDR 0
149 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
150 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
157 #ifndef CONFIG_SYS_RAMBOOT
158 #ifndef CONFIG_ENV_ADDR
159 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
160 CONFIG_SYS_MONITOR_LEN)
162 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
163 #ifndef CONFIG_ENV_OFFSET
164 #define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
167 /* Address and size of Redundant Environment Sector */
168 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
169 CONFIG_ENV_SECT_SIZE)
170 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
172 #else /* CFG_SYS_RAMBOOT */
173 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
174 #define CONFIG_ENV_SIZE 0x2000
175 #endif /* CFG_SYS_RAMBOOT */
178 #define CONFIG_SYS_I2C
179 #define CONFIG_SYS_NUM_I2C_BUSES 4
180 #define CONFIG_SYS_I2C_MAX_HOPS 1
181 #define CONFIG_SYS_I2C_FSL
182 #define CONFIG_SYS_FSL_I2C_SPEED 200000
183 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
184 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
185 #define CONFIG_SYS_I2C_OFFSET 0x3000
186 #define CONFIG_SYS_FSL_I2C2_SPEED 200000
187 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
188 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
189 #define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \
190 {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
191 {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
192 {1, {I2C_NULL_HOP} } }
194 #define CONFIG_KM_IVM_BUS 2 /* I2C2 (Mux-Port 1)*/
196 #if defined(CONFIG_CMD_NAND)
197 #define CONFIG_NAND_KMETER1
198 #define CONFIG_SYS_MAX_NAND_DEVICE 1
199 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE
203 * For booting Linux, the board info and command line data
204 * have to be in the first 8 MB of memory, since this is
205 * the maximum mapped by the Linux kernel during initialization.
207 #define CONFIG_SYS_BOOTMAPSZ (8 << 20)
212 #define CONFIG_SYS_HID0_INIT 0x000000000
213 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
214 HID0_ENABLE_INSTRUCTION_CACHE)
215 #define CONFIG_SYS_HID2 HID2_HBE
218 * Internal Definitions
220 #define BOOTFLASH_START 0xF0000000
222 #define CONFIG_KM_CONSOLE_TTY "ttyS0"
225 * Environment Configuration
227 #define CONFIG_ENV_OVERWRITE
228 #ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
229 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
232 #ifndef CONFIG_KM_DEF_ARCH
233 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
236 #define CONFIG_EXTRA_ENV_SETTINGS \
240 "prot off "__stringify(CONFIG_ENV_ADDR)" +0x40000 && " \
241 "era "__stringify(CONFIG_ENV_ADDR)" +0x40000\0" \
245 #if defined(CONFIG_UEC_ETH)
246 #define CONFIG_HAS_ETH0
252 #define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
257 #define CONFIG_SYS_DDR_SDRAM_CFG (\
258 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
262 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
264 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
265 CSCONFIG_ROW_BIT_13 | \
266 CSCONFIG_COL_BIT_10 | \
267 CSCONFIG_ODT_WR_ONLY_CURRENT)
269 #define CONFIG_SYS_DDR_CLK_CNTL (\
270 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
272 #define CONFIG_SYS_DDR_INTERVAL (\
273 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
274 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
276 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
278 #define CONFIG_SYS_DDRCDR (\
281 #define CONFIG_SYS_DDR_MODE 0x47860452
282 #define CONFIG_SYS_DDR_MODE2 0x8080c000
284 #define CONFIG_SYS_DDR_TIMING_0 (\
285 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
286 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
287 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
288 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
289 (0 << TIMING_CFG0_WWT_SHIFT) | \
290 (0 << TIMING_CFG0_RRT_SHIFT) | \
291 (0 << TIMING_CFG0_WRT_SHIFT) | \
292 (0 << TIMING_CFG0_RWT_SHIFT))
294 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
295 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
296 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
297 (3 << TIMING_CFG1_WRREC_SHIFT) | \
298 (7 << TIMING_CFG1_REFREC_SHIFT) | \
299 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
300 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
301 (3 << TIMING_CFG1_PRETOACT_SHIFT))
303 #define CONFIG_SYS_DDR_TIMING_2 (\
304 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
305 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
306 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
307 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
308 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
309 (5 << TIMING_CFG2_CPO_SHIFT) | \
310 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
312 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
315 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
318 * Local Bus Configuration & Clock Setup
320 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
321 #define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
322 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
325 * PAXE on the local bus CS3
327 #define CONFIG_SYS_PAXE_BASE 0xA0000000
328 #define CONFIG_SYS_PAXE_SIZE 256
330 #define CONFIG_SYS_BR3_PRELIM (\
331 CONFIG_SYS_PAXE_BASE | \
335 #define CONFIG_SYS_OR3_PRELIM (\