1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
12 * High Level Configuration Options
14 #define CONFIG_E300 1 /* E300 family */
15 #define CONFIG_MPC83xx 1 /* MPC83xx family */
17 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
22 #define CONFIG_SYS_SICRH (\
28 SICRH_IEEE1588_A_GPIO |\
31 SICRH_IEEE1588_B_GPIO |\
36 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
37 #define CONFIG_SYS_SICRL (\
42 SICRL_ETSEC1_GTX_CLK125) /* 0x00000000 */
47 #define CONFIG_SYS_IMMR 0xE0000000
52 #define CONFIG_FSL_SERDES
53 #define CONFIG_FSL_SERDES1 0xe3000
58 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
59 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
60 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
65 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
66 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
68 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
69 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
76 * Manually set up DDR parameters
77 * consist of one chip NT5TU64M16HG from NANYA
80 #define CONFIG_SYS_DDR_SIZE 128 /* MB */
82 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
83 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
84 | CSCONFIG_ODT_RD_NEVER \
85 | CSCONFIG_ODT_WR_ONLY_CURRENT \
86 | CSCONFIG_BANK_BIT_3 \
87 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
89 #define CONFIG_SYS_DDR_TIMING_3 0
90 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
91 | (0 << TIMING_CFG0_WRT_SHIFT) \
92 | (0 << TIMING_CFG0_RRT_SHIFT) \
93 | (0 << TIMING_CFG0_WWT_SHIFT) \
94 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
95 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
96 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
97 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
99 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
100 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
101 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
102 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
103 | (9 << TIMING_CFG1_REFREC_SHIFT) \
104 | (2 << TIMING_CFG1_WRREC_SHIFT) \
105 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
106 | (2 << TIMING_CFG1_WRTORD_SHIFT))
108 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
109 | (4 << TIMING_CFG2_CPO_SHIFT) \
110 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
111 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
112 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
113 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
114 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
116 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
117 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
119 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
120 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
124 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
125 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
126 | (0x0242 << SDRAM_MODE_SD_SHIFT))
127 /* ODT 150ohm CL=4, AL=0 on SDRAM */
128 #define CONFIG_SYS_DDR_MODE2 0x00000000
133 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
134 #define CONFIG_SYS_MEMTEST_END 0x07f00000
137 * The reserved memory
139 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
141 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
142 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
145 * Initial RAM Base Address Setup
147 #define CONFIG_SYS_INIT_RAM_LOCK 1
148 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
149 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
150 #define CONFIG_SYS_GBL_DATA_OFFSET \
151 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
154 * Local Bus Configuration & Clock Setup
156 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
157 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
158 #define CONFIG_SYS_LBC_LBCR 0x00040000
161 * FLASH on the Local Bus
164 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
165 #define CONFIG_FLASH_CFI_LEGACY
166 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
169 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
170 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
172 /* Window base at flash base */
173 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
174 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
176 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
177 | BR_PS_16 /* 16 bit port */ \
178 | BR_MS_GPCM /* MSEL = GPCM */ \
180 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
189 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
190 #define CONFIG_SYS_MAX_FLASH_SECT 135
192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
198 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
199 #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
201 /* Window base at FPGA base */
202 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
203 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB)
205 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
206 | BR_PS_16 /* 16 bit port */ \
207 | BR_MS_GPCM /* MSEL = GPCM */ \
209 #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
218 #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
219 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
221 #define CONFIG_SYS_FPGA_COUNT 1
223 #define CONFIG_SYS_MCLINK_MAX 3
225 #define CONFIG_SYS_FPGA_PTR \
226 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
231 #define CONFIG_SYS_NS16550_SERIAL
232 #define CONFIG_SYS_NS16550_REG_SIZE 1
233 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
235 #define CONFIG_SYS_BAUDRATE_TABLE \
236 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
238 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
239 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
241 /* Pass open firmware flat tree */
244 #define CONFIG_SYS_I2C
245 #define CONFIG_SYS_I2C_FSL
246 #define CONFIG_SYS_FSL_I2C_SPEED 400000
247 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
248 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
250 #define CONFIG_PCA953X /* NXP PCA9554 */
251 #define CONFIG_PCA9698 /* NXP PCA9698 */
253 #define CONFIG_SYS_I2C_IHS
254 #define CONFIG_SYS_I2C_IHS_CH0
255 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000
256 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
257 #define CONFIG_SYS_I2C_IHS_CH1
258 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000
259 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
260 #define CONFIG_SYS_I2C_IHS_CH2
261 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000
262 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
263 #define CONFIG_SYS_I2C_IHS_CH3
264 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000
265 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
267 #ifdef CONFIG_HRCON_DH
268 #define CONFIG_SYS_I2C_IHS_DUAL
269 #define CONFIG_SYS_I2C_IHS_CH0_1
270 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
271 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
272 #define CONFIG_SYS_I2C_IHS_CH1_1
273 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
274 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
275 #define CONFIG_SYS_I2C_IHS_CH2_1
276 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
277 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
278 #define CONFIG_SYS_I2C_IHS_CH3_1
279 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
280 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
284 * Software (bit-bang) I2C driver configuration
286 #define CONFIG_SYS_I2C_SOFT
287 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
288 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
289 #define I2C_SOFT_DECLARATIONS2
290 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
291 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
292 #define I2C_SOFT_DECLARATIONS3
293 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
294 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
295 #define I2C_SOFT_DECLARATIONS4
296 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
297 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
298 #define I2C_SOFT_DECLARATIONS5
299 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
300 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
301 #define I2C_SOFT_DECLARATIONS6
302 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
303 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
304 #define I2C_SOFT_DECLARATIONS7
305 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
306 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
307 #define I2C_SOFT_DECLARATIONS8
308 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
309 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
311 #ifdef CONFIG_HRCON_DH
312 #define I2C_SOFT_DECLARATIONS9
313 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
314 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
315 #define I2C_SOFT_DECLARATIONS10
316 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
317 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
318 #define I2C_SOFT_DECLARATIONS11
319 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
320 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
321 #define I2C_SOFT_DECLARATIONS12
322 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
323 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
326 #ifdef CONFIG_HRCON_DH
327 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
328 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
329 #define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \
332 #define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12}
333 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
334 #define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \
339 void fpga_gpio_set(unsigned int bus, int pin);
340 void fpga_gpio_clear(unsigned int bus, int pin);
341 int fpga_gpio_get(unsigned int bus, int pin);
342 void fpga_control_set(unsigned int bus, int pin);
343 void fpga_control_clear(unsigned int bus, int pin);
346 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
347 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
348 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
350 #ifdef CONFIG_HRCON_DH
353 if (I2C_ADAP_HWNR > 7) \
354 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
356 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
359 #define I2C_ACTIVE { }
361 #define I2C_TRISTATE { }
363 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
364 #define I2C_SDA(bit) \
367 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
369 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
371 #define I2C_SCL(bit) \
374 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
376 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
378 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
381 * Software (bit-bang) MII driver configuration
383 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
384 #define CONFIG_BITBANGMII_MULTI
389 #define CONFIG_SYS_OSD_SCREENS 1
390 #define CONFIG_SYS_DP501_DIFFERENTIAL
391 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
393 #ifdef CONFIG_HRCON_DH
394 #define CONFIG_SYS_OSD_DH
399 * Addresses are mapped 1-1.
401 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
402 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
403 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
404 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
405 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
406 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
407 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
409 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
411 /* enable PCIE clock */
412 #define CONFIG_SYS_SCCR_PCIEXP1CM 1
414 #define CONFIG_PCI_INDIRECT_BRIDGE
417 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
418 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
423 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
424 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
427 * TSEC ethernet configuration
430 #define CONFIG_TSEC1_NAME "eTSEC0"
431 #define TSEC1_PHY_ADDR 1
432 #define TSEC1_PHYIDX 0
433 #define TSEC1_FLAGS TSEC_GIGABIT
435 /* Options are: eTSEC[0-1] */
436 #define CONFIG_ETHPRIME "eTSEC0"
442 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
443 CONFIG_SYS_MONITOR_LEN)
444 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
445 #define CONFIG_ENV_SIZE 0x2000
446 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
447 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
449 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
452 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
453 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
456 * Command line configuration.
460 * Miscellaneous configurable options
462 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
463 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
467 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
470 * For booting Linux, the board info and command line data
471 * have to be in the first 256 MB of memory, since this is
472 * the maximum mapped by the Linux kernel during initialization.
474 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
479 #define CONFIG_SYS_HID0_INIT 0x000000000
480 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
481 HID0_ENABLE_INSTRUCTION_CACHE | \
482 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
483 #define CONFIG_SYS_HID2 HID2_HBE
489 /* DDR: cache cacheable */
490 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
492 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
494 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
495 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
497 /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
498 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \
499 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
500 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
502 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
503 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
505 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
506 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
508 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
510 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
511 BATL_CACHEINHIBIT | \
513 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
515 /* Stack in dcache: cacheable, no memory coherence */
516 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
517 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
519 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
520 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
523 * Environment Configuration
526 #define CONFIG_ENV_OVERWRITE
528 #if defined(CONFIG_TSEC_ENET)
529 #define CONFIG_HAS_ETH0
532 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
535 #define CONFIG_HOSTNAME "hrcon"
536 #define CONFIG_ROOTPATH "/opt/nfsroot"
537 #define CONFIG_BOOTFILE "uImage"
539 #define CONFIG_PREBOOT /* enable preboot variable */
541 #define CONFIG_EXTRA_ENV_SETTINGS \
543 "consoledev=ttyS1\0" \
544 "u-boot=u-boot.bin\0" \
545 "kernel_addr=1000000\0" \
546 "fdt_addr=C00000\0" \
547 "fdtfile=hrcon.dtb\0" \
548 "load=tftp ${loadaddr} ${u-boot}\0" \
549 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
550 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
551 " +${filesize};cp.b ${fileaddr} " \
552 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
553 "upd=run load update\0" \
555 #define CONFIG_NFSBOOTCOMMAND \
556 "setenv bootargs root=/dev/nfs rw " \
557 "nfsroot=$serverip:$rootpath " \
558 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
559 "console=$consoledev,$baudrate $othbootargs;" \
560 "tftp ${kernel_addr} $bootfile;" \
561 "tftp ${fdt_addr} $fdtfile;" \
562 "bootm ${kernel_addr} - ${fdt_addr}"
564 #define CONFIG_MMCBOOTCOMMAND \
565 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
566 "console=$consoledev,$baudrate $othbootargs;" \
567 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
568 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
569 "bootm ${kernel_addr} - ${fdt_addr}"
571 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
573 #endif /* __CONFIG_H */