include/configs/caddy2.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * esd vme8349 U-Boot configuration file
   4  * Copyright (c) 2008, 2009 esd gmbh Hannover Germany
   5  *
   6  * (C) Copyright 2006-2010
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * reinhard.arlt@esd-electronics.de
  10  * Based on the MPC8349EMDS config.
  11  */
  12
  13 /*
  14  * vme8349 board configuration file.
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 /*
  21  * High Level Configuration Options
  22  */
  23 #define CONFIG_E300             1       /* E300 Family */
  24
  25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */
  26 #undef CONFIG_MPC83XX_PCI2              /* support for 2nd PCI controller */
  27
  28 #undef CONFIG_SYS_DRAM_TEST                     /* memory test, takes time */
  29 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  30 #define CONFIG_SYS_MEMTEST_END          0x00100000
  31
  32 /*
  33  * DDR Setup
  34  */
  35 #define CONFIG_DDR_ECC                  /* only for ECC DDR module */
  36 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  37 #define CONFIG_SPD_EEPROM
  38 #define SPD_EEPROM_ADDRESS              0x54
  39 #define CONFIG_SYS_READ_SPD             vme8349_read_spd
  40 #define CONFIG_SYS_83XX_DDR_USES_CS0    /* esd; Fsl board uses CS2/CS3 */
  41
  42 /*
  43  * 32-bit data path mode.
  44  *
  45  * Please note that using this mode for devices with the real density of 64-bit
  46  * effectively reduces the amount of available memory due to the effect of
  47  * wrapping around while translating address to row/columns, for example in the
  48  * 256MB module the upper 128MB get aliased with contents of the lower
  49  * 128MB); normally this define should be used for devices with real 32-bit
  50  * data path.
  51  */
  52 #undef CONFIG_DDR_32BIT
  53
  54 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* DDR is sys memory*/
  55 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  56                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
  57 #define CONFIG_DDR_2T_TIMING
  58 #define CONFIG_SYS_DDRCDR               (DDRCDR_DHC_EN \
  59                                         | DDRCDR_ODT \
  60                                         | DDRCDR_Q_DRN)
  61                                         /* 0x80080001 */
  62
  63 /*
  64  * FLASH on the Local Bus
  65  */
  66 #define CONFIG_SYS_FLASH_BASE           0xffc00000      /* start of FLASH   */
  67 #define CONFIG_SYS_FLASH_SIZE           4               /* flash size in MB */
  68
  69
  70 #define CONFIG_SYS_WINDOW1_BASE         0xf0000000
  71
  72
  73 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  74 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device*/
  75
  76 #undef CONFIG_SYS_FLASH_CHECKSUM
  77 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase TO (ms) */
  78 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write TO (ms) */
  79
  80 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  81
  82 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  83 #define CONFIG_SYS_RAMBOOT
  84 #else
  85 #undef CONFIG_SYS_RAMBOOT
  86 #endif
  87
  88 #define CONFIG_SYS_INIT_RAM_LOCK        1
  89 #define CONFIG_SYS_INIT_RAM_ADDR        0xF7000000      /* Initial RAM addr */
  90 #define CONFIG_SYS_INIT_RAM_SIZE                0x1000          /* size */
  91
  92 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  93                                          GENERATED_GBL_DATA_SIZE)
  94 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  95
  96 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB */
  97 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Malloc size */
  98
  99 /*
 100  * Local Bus LCRR and LBCR regs
 101  *    LCRR:  no DLL bypass, Clock divider is 4
 102  * External Local Bus rate is
 103  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 104  */
 105 #define CONFIG_SYS_LBC_LBCR     0x00000000
 106
 107 #undef CONFIG_SYS_LB_SDRAM      /* if board has SDRAM on local bus */
 108
 109 /*
 110  * Serial Port
 111  */
 112 #define CONFIG_SYS_NS16550_SERIAL
 113 #define CONFIG_SYS_NS16550_REG_SIZE     1
 114 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 115
 116 #define CONFIG_SYS_BAUDRATE_TABLE  \
 117                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 118
 119 #define CONFIG_SYS_NS16550_COM1         (CONFIG_SYS_IMMR + 0x4500)
 120 #define CONFIG_SYS_NS16550_COM2         (CONFIG_SYS_IMMR + 0x4600)
 121
 122 /* I2C */
 123 #define CONFIG_SYS_I2C
 124 #define CONFIG_SYS_I2C_FSL
 125 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 126 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 127 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 128 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 129 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 130 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 131 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 132 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 133
 134 #define CONFIG_SYS_I2C_8574_ADDR2       0x20    /* I2C1, PCF8574 */
 135
 136 /* TSEC */
 137 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 138 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 139 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 140 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 141
 142 /*
 143  * General PCI
 144  * Addresses are mapped 1-1.
 145  */
 146 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 147 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 148 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 149 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 150 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 151 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 152 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 153 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 154 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 155
 156 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 157 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 158 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 159 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 160 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 161 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 162 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 163 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 164 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 165
 166 #if defined(CONFIG_PCI)
 167
 168 #undef CONFIG_EEPRO100
 169 #undef CONFIG_TULIP
 170
 171 #if !defined(CONFIG_PCI_PNP)
 172         #define PCI_ENET0_IOADDR        0xFIXME
 173         #define PCI_ENET0_MEMADDR       0xFIXME
 174         #define PCI_IDSEL_NUMBER        0xFIXME
 175 #endif
 176
 177 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 178 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 179
 180 #endif  /* CONFIG_PCI */
 181
 182 /*
 183  * TSEC configuration
 184  */
 185
 186 #if defined(CONFIG_TSEC_ENET)
 187
 188 #define CONFIG_GMII                     /* MII PHY management */
 189 #define CONFIG_TSEC1
 190 #define CONFIG_TSEC1_NAME       "TSEC0"
 191 #define CONFIG_TSEC2
 192 #define CONFIG_TSEC2_NAME       "TSEC1"
 193 #define CONFIG_PHY_M88E1111
 194 #define TSEC1_PHY_ADDR          0x08
 195 #define TSEC2_PHY_ADDR          0x10
 196 #define TSEC1_PHYIDX            0
 197 #define TSEC2_PHYIDX            0
 198 #define TSEC1_FLAGS             TSEC_GIGABIT
 199 #define TSEC2_FLAGS             TSEC_GIGABIT
 200
 201 /* Options are: TSEC[0-1] */
 202 #define CONFIG_ETHPRIME         "TSEC0"
 203
 204 #endif  /* CONFIG_TSEC_ENET */
 205
 206 /*
 207  * Environment
 208  */
 209 #ifndef CONFIG_SYS_RAMBOOT
 210         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + 0xc0000)
 211         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 212         #define CONFIG_ENV_SIZE         0x2000
 213
 214 /* Address and size of Redundant Environment Sector     */
 215 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 216 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 217
 218 #else
 219         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 220         #define CONFIG_ENV_SIZE         0x2000
 221 #endif
 222
 223 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 224 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 225
 226 /*
 227  * BOOTP options
 228  */
 229 #define CONFIG_BOOTP_BOOTFILESIZE
 230
 231 /*
 232  * Command line configuration.
 233  */
 234 #define CONFIG_SYS_RTC_BUS_NUM  0x01
 235 #define CONFIG_SYS_I2C_RTC_ADDR 0x32
 236 #define CONFIG_RTC_RX8025
 237
 238 /* Pass Ethernet MAC to VxWorks */
 239 #define CONFIG_SYS_VXWORKS_MAC_PTR      0x000043f0
 240
 241 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 242
 243 /*
 244  * Miscellaneous configurable options
 245  */
 246 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 247
 248 /*
 249  * For booting Linux, the board info and command line data
 250  * have to be in the first 256 MB of memory, since this is
 251  * the maximum mapped by the Linux kernel during initialization.
 252  */
 253 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)     /* Init Memory map for Linux*/
 254
 255 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 256
 257 /* System IO Config */
 258 #define CONFIG_SYS_SICRH 0
 259 #define CONFIG_SYS_SICRL SICRL_LDP_A
 260
 261 #define CONFIG_SYS_GPIO1_PRELIM
 262 #define CONFIG_SYS_GPIO1_DIR    0x00100000
 263 #define CONFIG_SYS_GPIO1_DAT    0x00100000
 264
 265 #define CONFIG_SYS_GPIO2_PRELIM
 266 #define CONFIG_SYS_GPIO2_DIR    0x78900000
 267 #define CONFIG_SYS_GPIO2_DAT    0x70100000
 268
 269 #ifdef CONFIG_PCI
 270 #define CONFIG_PCI_INDIRECT_BRIDGE
 271 #endif
 272
 273 #if defined(CONFIG_CMD_KGDB)
 274 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 275 #endif
 276
 277 /*
 278  * Environment Configuration
 279  */
 280 #define CONFIG_ENV_OVERWRITE
 281
 282 #if defined(CONFIG_TSEC_ENET)
 283 #define CONFIG_HAS_ETH0
 284 #define CONFIG_HAS_ETH1
 285 #endif
 286
 287 #define CONFIG_HOSTNAME         "VME8349"
 288 #define CONFIG_ROOTPATH         "/tftpboot/rootfs"
 289 #define CONFIG_BOOTFILE         "uImage"
 290
 291 #define CONFIG_LOADADDR         800000  /* def location for tftp and bootm */
 292
 293 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 294         "netdev=eth0\0"                                                 \
 295         "hostname=vme8349\0"                                            \
 296         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 297                 "nfsroot=${serverip}:${rootpath}\0"                     \
 298         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 299         "addip=setenv bootargs ${bootargs} "                            \
 300                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 301                 ":${hostname}:${netdev}:off panic=1\0"                  \
 302         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 303         "flash_nfs=run nfsargs addip addtty;"                           \
 304                 "bootm ${kernel_addr}\0"                                \
 305         "flash_self=run ramargs addip addtty;"                          \
 306                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 307         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 308                 "bootm\0"                                               \
 309         "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0"              \
 310         "update=protect off fff00000 fff3ffff; "                        \
 311                 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \
 312         "upd=run load update\0"                                         \
 313         "fdtaddr=780000\0"                                              \
 314         "fdtfile=vme8349.dtb\0"                                         \
 315         ""
 316
 317 #define CONFIG_NFSBOOTCOMMAND                                           \
 318         "setenv bootargs root=/dev/nfs rw "                             \
 319                 "nfsroot=$serverip:$rootpath "                          \
 320                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 321                                                         "$netdev:off "  \
 322                 "console=$consoledev,$baudrate $othbootargs;"           \
 323         "tftp $loadaddr $bootfile;"                                     \
 324         "tftp $fdtaddr $fdtfile;"                                       \
 325         "bootm $loadaddr - $fdtaddr"
 326
 327 #define CONFIG_RAMBOOTCOMMAND                                           \
 328         "setenv bootargs root=/dev/ram rw "                             \
 329                 "console=$consoledev,$baudrate $othbootargs;"           \
 330         "tftp $ramdiskaddr $ramdiskfile;"                               \
 331         "tftp $loadaddr $bootfile;"                                     \
 332         "tftp $fdtaddr $fdtfile;"                                       \
 333         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 334
 335 #define CONFIG_BOOTCOMMAND      "run flash_self"
 336
 337 #ifndef __ASSEMBLY__
 338 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen,
 339                      unsigned char *buffer, int len);
 340 #endif
 341
 342 #endif  /* __CONFIG_H */